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Convert RTLIL::unescape_id of IdString to unescape()

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This commit is contained in:
Miodrag Milanovic 2026-05-15 15:54:07 +02:00
parent 8bbc3c359c
commit 75dcbe03c6
35 changed files with 636 additions and 114 deletions
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6
passes/cmds/icell_liberty.cc
View file

@ -71,10 +71,10 @@ struct LibertyStubber {
std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
std::string clock_pin_name = "";
for (auto x : sorted_ports) {
std::string port_name = RTLIL::unescape_id(x);
std::string port_name = x.unescape();
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
f << "\t\tpin (" << x.unescape() << ") {\n";
if (is_input && !is_output) {
i.item("direction", "input");
} else if (!is_input && is_output) {
@ -132,7 +132,7 @@ struct LibertyStubber {
for (auto x : derived->ports) {
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
f << "\t\tpin (" << x.unescape() << ") {\n";
if (is_input && !is_output) {
f << "\t\t\tdirection : input;\n";
} else if (!is_input && is_output) {

2
passes/cmds/portarcs.cc
View file

@ -244,7 +244,7 @@ struct PortarcsPass : Pass {
if (draw_mode) {
auto bit_str = [](SigBit bit) {
return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
return stringf("%s%d", bit.wire, bit.offset);
};
std::vector<std::string> headings;

2
passes/cmds/rename.cc
View file

@ -621,7 +621,7 @@ struct RenamePass : public Pass {
RTLIL::Module *module_to_rename = nullptr;
for (auto module : design->modules())
if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
if (module->name == from_name || module->name.unescape() == from_name) {
module_to_rename = module;
break;
}

2
passes/cmds/show.cc
View file

@ -549,7 +549,7 @@ struct ShowWorker
net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
}
std::string proc_src = RTLIL::unescape_id(proc->name);
std::string proc_src = proc->name.unescape();
if (proc->attributes.count(ID::src) > 0)
proc_src = proc->attributes.at(ID::src).decode_string();
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());

2
passes/cmds/wrapcell.cc
View file

@ -227,7 +227,7 @@ struct WrapcellPass : Pass {
if (!unused_outputs.empty()) {
context.unused_outputs += "_unused";
for (auto chunk : collect_chunks(unused_outputs))
context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
context.unused_outputs += "_" + chunk.format(cell).unescape();
}
std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);

520
passes/equiv/equiv_make.cc.orig Normal file
View file

@ -0,0 +1,520 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct EquivMakeWorker
{
Module *gold_mod, *gate_mod, *equiv_mod;
pool<IdString> wire_names, cell_names;
CellTypes ct;
bool inames;
vector<string> blacklists;
vector<string> encfiles;
bool make_assert;
pool<IdString> blacklist_names;
dict<IdString, dict<Const, Const>> encdata;
pool<SigBit> undriven_bits;
SigMap assign_map;
void read_blacklists()
{
for (auto fn : blacklists)
{
std::ifstream f(fn);
if (f.fail())
log_cmd_error("Can't open blacklist file '%s'!\n", fn);
string line, token;
while (std::getline(f, line)) {
while (1) {
token = next_token(line);
if (token.empty())
break;
blacklist_names.insert(RTLIL::escape_id(token));
}
}
}
}
void read_encfiles()
{
for (auto fn : encfiles)
{
std::ifstream f(fn);
if (f.fail())
log_cmd_error("Can't open encfile '%s'!\n", fn);
dict<Const, Const> *ed = nullptr;
string line, token;
while (std::getline(f, line))
{
token = next_token(line);
if (token.empty() || token[0] == '#')
continue;
if (token == ".fsm") {
IdString modname = RTLIL::escape_id(next_token(line));
(void)modname;
IdString signame = RTLIL::escape_id(next_token(line));
if (encdata.count(signame))
log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn);
encdata[signame] = dict<Const, Const>();
ed = &encdata[signame];
continue;
}
if (token == ".map") {
Const gold_bits = Const::from_string(next_token(line));
Const gate_bits = Const::from_string(next_token(line));
(*ed)[gold_bits] = gate_bits;
continue;
}
log_cmd_error("Syntax error in encfile '%s'!\n", fn);
}
}
}
void copy_to_equiv()
{
Module *gold_clone = gold_mod->clone();
Module *gate_clone = gate_mod->clone();
for (auto it : gold_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gold_clone->rename(it, it->name.str() + "_gold");
}
for (auto it : gold_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, it->name.str() + "_gold");
}
for (auto it : gate_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gate_clone->rename(it, it->name.str() + "_gate");
}
for (auto it : gate_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, it->name.str() + "_gate");
}
gold_clone->cloneInto(equiv_mod);
gate_clone->cloneInto(equiv_mod);
delete gold_clone;
delete gate_clone;
}
void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig)
{
auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig);
equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1);
}
void find_same_wires()
{
SigMap assign_map(equiv_mod);
SigMap rd_signal_map;
SigPool primary_inputs;
// list of cells without added $equiv cells
auto cells_list = equiv_mod->cells().to_vector();
for (auto id : wire_names)
{
IdString gold_id = id.str() + "_gold";
IdString gate_id = id.str() + "_gate";
Wire *gold_wire = equiv_mod->wire(gold_id);
Wire *gate_wire = equiv_mod->wire(gate_id);
if (encdata.count(id))
{
log("Creating encoder/decoder for signal %s.\n", id.unescape());
Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width);
Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width);
SigSpec dec_a, dec_b, dec_s;
SigSpec enc_a, enc_b, enc_s;
dec_a = SigSpec(State::Sx, dec_wire->width);
enc_a = SigSpec(State::Sx, enc_wire->width);
for (auto &it : encdata.at(id))
{
SigSpec dec_sig = gate_wire, dec_pat = it.second;
SigSpec enc_sig = dec_wire, enc_pat = it.first;
if (GetSize(dec_sig) != GetSize(dec_pat))
log_error("Invalid pattern %s for signal %s of size %d!\n",
log_signal(dec_pat), log_signal(dec_sig), GetSize(dec_sig));
if (GetSize(enc_sig) != GetSize(enc_pat))
log_error("Invalid pattern %s for signal %s of size %d!\n",
log_signal(enc_pat), log_signal(enc_sig), GetSize(enc_sig));
SigSpec reduced_dec_sig, reduced_dec_pat;
for (int i = 0; i < GetSize(dec_sig); i++)
if (dec_pat[i] == State::S0 || dec_pat[i] == State::S1) {
reduced_dec_sig.append(dec_sig[i]);
reduced_dec_pat.append(dec_pat[i]);
}
SigSpec reduced_enc_sig, reduced_enc_pat;
for (int i = 0; i < GetSize(enc_sig); i++)
if (enc_pat[i] == State::S0 || enc_pat[i] == State::S1) {
reduced_enc_sig.append(enc_sig[i]);
reduced_enc_pat.append(enc_pat[i]);
}
SigSpec dec_result = it.first;
for (auto &bit : dec_result)
if (bit != State::S1) bit = State::S0;
SigSpec enc_result = it.second;
for (auto &bit : enc_result)
if (bit != State::S1) bit = State::S0;
SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
dec_s.append(dec_eq);
enc_s.append(enc_eq);
dec_b.append(dec_result);
enc_b.append(enc_result);
}
equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire);
equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire);
rd_signal_map.add(assign_map(gate_wire), enc_wire);
gate_wire = dec_wire;
}
if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) {
if (gold_wire && gold_wire->port_id)
log_error("Can't match gold port `%s' to a gate port.\n", gold_wire);
if (gate_wire && gate_wire->port_id)
log_error("Can't match gate port `%s' to a gold port.\n", gate_wire);
continue;
}
log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
gold_wire, log_signal(assign_map(gold_wire)),
gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
if (gold_wire->port_output || gate_wire->port_output)
{
gold_wire->port_input = false;
gate_wire->port_input = false;
gold_wire->port_output = false;
gate_wire->port_output = false;
Wire *wire = equiv_mod->addWire(id, gold_wire->width);
wire->port_output = true;
if (make_assert)
{
add_eq_assertion(gold_wire, gate_wire);
equiv_mod->connect(wire, gold_wire);
}
else
{
for (int i = 0; i < wire->width; i++)
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
}
rd_signal_map.add(assign_map(gold_wire), wire);
rd_signal_map.add(assign_map(gate_wire), wire);
}
else
if (gold_wire->port_input || gate_wire->port_input)
{
Wire *wire = equiv_mod->addWire(id, gold_wire->width);
wire->port_input = true;
gold_wire->port_input = false;
gate_wire->port_input = false;
equiv_mod->connect(gold_wire, wire);
equiv_mod->connect(gate_wire, wire);
primary_inputs.add(assign_map(gold_wire));
primary_inputs.add(assign_map(gate_wire));
primary_inputs.add(wire);
}
else
{
if (make_assert)
add_eq_assertion(gold_wire, gate_wire);
else {
Wire *wire = equiv_mod->addWire(id, gold_wire->width);
SigSpec rdmap_gold, rdmap_gate, rdmap_equiv;
for (int i = 0; i < wire->width; i++) {
if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
continue;
}
if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
continue;
}
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
rdmap_gold.append(SigBit(gold_wire, i));
rdmap_gate.append(SigBit(gate_wire, i));
rdmap_equiv.append(SigBit(wire, i));
}
rd_signal_map.add(rdmap_gold, rdmap_equiv);
rd_signal_map.add(rdmap_gate, rdmap_equiv);
}
}
}
for (auto c : cells_list)
for (auto &conn : c->connections())
if (!ct.cell_output(c->type, conn.first)) {
SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig);
for (int i = 0; i < GetSize(old_sig); i++)
if (primary_inputs.check(old_sig[i]))
new_sig[i] = old_sig[i];
if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n",
conn.first.unescape(), c, c->type.unescape(),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
}
}
equiv_mod->fixup_ports();
}
void find_same_cells()
{
SigMap assign_map(equiv_mod);
for (auto id : cell_names)
{
IdString gold_id = id.str() + "_gold";
IdString gate_id = id.str() + "_gate";
Cell *gold_cell = equiv_mod->cell(gold_id);
Cell *gate_cell = equiv_mod->cell(gate_id);
if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
try_next_cell_name:
continue;
for (auto gold_conn : gold_cell->connections())
if (!gate_cell->connections().count(gold_conn.first))
goto try_next_cell_name;
log("Presumably equivalent cells: %s %s (%s) -> %s\n",
gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
for (auto gold_conn : gold_cell->connections())
{
SigSpec gold_sig = assign_map(gold_conn.second);
SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
if (ct.cell_output(gold_cell->type, gold_conn.first)) {
equiv_mod->connect(gate_sig, gold_sig);
continue;
}
if (make_assert)
{
if (gold_sig != gate_sig)
add_eq_assertion(gold_sig, gate_sig);
}
else
{
for (int i = 0; i < GetSize(gold_sig); i++)
if (gold_sig[i] != gate_sig[i]) {
Wire *w = equiv_mod->addWire(NEW_ID);
equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
gold_sig[i] = w;
}
}
gold_cell->setPort(gold_conn.first, gold_sig);
}
equiv_mod->remove(gate_cell);
equiv_mod->rename(gold_cell, id);
}
}
void find_undriven_nets(bool mark)
{
undriven_bits.clear();
assign_map.set(equiv_mod);
for (auto wire : equiv_mod->wires()) {
for (auto bit : assign_map(wire))
if (bit.wire)
undriven_bits.insert(bit);
}
for (auto wire : equiv_mod->wires()) {
if (wire->port_input)
for (auto bit : assign_map(wire))
undriven_bits.erase(bit);
}
for (auto cell : equiv_mod->cells()) {
for (auto &conn : cell->connections())
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
undriven_bits.erase(bit);
}
if (mark) {
SigSpec undriven_sig(undriven_bits);
undriven_sig.sort_and_unify();
for (auto chunk : undriven_sig.chunks()) {
log("Setting undriven nets to undef: %s\n", log_signal(chunk));
equiv_mod->connect(chunk, SigSpec(State::Sx, chunk.width));
}
}
}
void run()
{
copy_to_equiv();
find_undriven_nets(false);
find_same_wires();
find_same_cells();
find_undriven_nets(true);
}
};
struct EquivMakePass : public Pass {
EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" equiv_make [options] gold_module gate_module equiv_module\n");
log("\n");
log("This creates a module annotated with $equiv cells from two presumably\n");
log("equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'\n");
log("to work with the created equivalent checking module.\n");
log("\n");
log(" -inames\n");
log(" Also match cells and wires with $... names.\n");
log("\n");
log(" -blacklist <file>\n");
log(" Do not match cells or signals that match the names in the file.\n");
log("\n");
log(" -encfile <file>\n");
log(" Match FSM encodings using the description from the file.\n");
log(" See 'help fsm_recode' for details.\n");
log("\n");
log(" -make_assert\n");
log(" Check equivalence with $assert cells instead of $equiv.\n");
log(" $eqx (===) is used to compare signals.");
log("\n");
log("Note: The circuit created by this command is not a miter (with something like\n");
log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
EquivMakeWorker worker;
worker.ct.setup(design);
worker.inames = false;
worker.make_assert = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-inames") {
worker.inames = true;
continue;
}
if (args[argidx] == "-blacklist" && argidx+1 < args.size()) {
worker.blacklists.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
worker.encfiles.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-make_assert") {
worker.make_assert = true;
continue;
}
break;
}
if (argidx+3 != args.size())
log_cmd_error("Invalid number of arguments.\n");
worker.gold_mod = design->module(RTLIL::escape_id(args[argidx]));
worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1]));
worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2]));
if (worker.gold_mod == nullptr)
log_cmd_error("Can't find gold module %s.\n", args[argidx]);
if (worker.gate_mod == nullptr)
log_cmd_error("Can't find gate module %s.\n", args[argidx+1]);
if (worker.equiv_mod != nullptr)
log_cmd_error("Equiv module %s already exists.\n", args[argidx+2]);
if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
worker.read_blacklists();
worker.read_encfiles();
log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
worker.run();
}
} EquivMakePass;
PRIVATE_NAMESPACE_END

4
passes/fsm/fsm_recode.cc
View file

@ -39,7 +39,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
for (int i = fsm_data.state_bits-1; i >= 0; i--)
fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i);
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(),
prefix, RTLIL::unescape_id(module->name).c_str());
prefix, module->name.unescape().c_str());
fprintf(f, "set_fsm_encoding {");
for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
@ -49,7 +49,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(name).c_str(),
prefix, RTLIL::unescape_id(module->name).c_str());
prefix, module->name.unescape().c_str());
}
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding)

6
passes/hierarchy/flatten.cc
View file

@ -281,13 +281,13 @@ struct FlattenWorker
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second);
scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
}
for (auto const &attr : tpl->attributes)
scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first)), attr.second);
scopeinfo->attributes.emplace(stringf("\\module_%s", attr.first.unescape()), attr.second);
scopeinfo->attributes.emplace(ID(module), RTLIL::unescape_id(tpl->name));
scopeinfo->attributes.emplace(ID(module), tpl->name.unescape());
}
module->remove(cell);

6
passes/hierarchy/hierarchy.cc
View file

@ -50,7 +50,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
continue;
for (auto &pattern : celltypes)
if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
if (patmatch(pattern.c_str(), cell->type.unescape().c_str()))
found_celltypes.insert(cell->type);
}
@ -100,7 +100,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
while (portnames.size() > 0) {
RTLIL::IdString portname = *portnames.begin();
for (auto &decl : portdecls)
if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) {
generate_port_decl_t d = decl;
d.portname = portname.str();
d.index = *indices.begin();
@ -397,7 +397,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
};
for (auto &ext : extensions_list) {
std::string filename = dir + "/" + RTLIL::unescape_id(cell.type) + ext.first;
std::string filename = dir + "/" + cell.type.unescape() + ext.first;
if (!check_file_exists(filename))
continue;

2
passes/sat/cutpoint.cc
View file

@ -159,7 +159,7 @@ struct CutpointPass : public Pass {
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second);
scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second);
}
}

4
passes/sat/expose.cc
View file

@ -632,7 +632,7 @@ struct ExposePass : public Pass {
if (!p->port_input && !p->port_output)
continue;
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width);
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + p->name.unescape(), p->width);
if (p->port_input)
w->port_output = true;
if (p->port_output)
@ -654,7 +654,7 @@ struct ExposePass : public Pass {
{
for (auto &it : cell->connections())
{
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size());
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + it.first.unescape(), it.second.size());
if (ct.cell_input(cell->type, it.first))
w->port_output = true;
if (ct.cell_output(cell->type, it.first))

12
passes/sat/miter.cc
View file

@ -143,7 +143,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
{
if (gold_cross_ports.count(gold_wire))
{
SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
SigSpec w = miter_module->addWire("\\cross_" + gold_wire->name.unescape(), gold_wire->width);
gold_cell->setPort(gold_wire->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w));
@ -159,7 +159,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_input)
{
RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
RTLIL::Wire *w = miter_module->addWire("\\in_" + gold_wire->name.unescape(), gold_wire->width);
w->port_input = true;
gold_cell->setPort(gold_wire->name, w);
@ -168,10 +168,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_output)
{
RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + gold_wire->name.unescape(), gold_wire->width);
w_gold->port_output = flag_make_outputs;
RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + gold_wire->name.unescape(), gold_wire->width);
w_gate->port_output = flag_make_outputs;
gold_cell->setPort(gold_wire->name, w_gold);
@ -244,7 +244,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_outcmp)
{
RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name));
RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + gold_wire->name.unescape());
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@ -252,7 +252,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_cover)
{
auto cover_condition = miter_module->Not(NEW_ID, this_condition);
miter_module->addCover("\\cover_" + RTLIL::unescape_id(gold_wire->name), cover_condition, State::S1);
miter_module->addCover("\\cover_" + gold_wire->name.unescape(), cover_condition, State::S1);
}
all_conditions.append(this_condition);

40
passes/sat/sim.cc
View file

@ -275,9 +275,9 @@ struct SimInstance
}
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
fstHandle id = shared->fst->getHandle(scope + "." + wire->name.unescape());
if (id==0 && wire->name.isPublic())
log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)));
log_warning("Unable to find wire %s in input file.\n", (scope + "." + wire->name.unescape()));
fst_handles[wire] = id;
}
@ -316,7 +316,7 @@ struct SimInstance
Module *mod = module->design->module(cell->type);
if (mod != nullptr) {
dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
dirty_children.insert(new SimInstance(shared, scope + "." + cell->name.unescape(), mod, cell, this));
}
for (auto &port : cell->connections()) {
@ -1209,7 +1209,7 @@ struct SimInstance
}
}
if (!found)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + sig_y.as_wire()->name.unescape()));
}
}
}
@ -1495,7 +1495,7 @@ struct SimWorker : SimShared
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
@ -1507,7 +1507,7 @@ struct SimWorker : SimShared
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
@ -1517,9 +1517,9 @@ struct SimWorker : SimShared
for (auto wire : topmod->wires()) {
if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
top->fst_inputs[wire] = id;
}
}
@ -2114,12 +2114,12 @@ struct SimWorker : SimShared
std::stringstream f;
if (wire->width==1)
f << stringf("%s", RTLIL::unescape_id(wire->name));
f << stringf("%s", wire);
else
if (wire->upto)
f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name));
f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, wire);
else
f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name));
f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, wire);
return f.str();
}
@ -2127,7 +2127,7 @@ struct SimWorker : SimShared
{
std::stringstream f;
for(auto item=signals.begin();item!=signals.end();item++)
f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name));
f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), item->first);
return f.str();
}
@ -2151,7 +2151,7 @@ struct SimWorker : SimShared
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
@ -2164,7 +2164,7 @@ struct SimWorker : SimShared
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
fstHandle id = fst->getHandle(scope + "." + portname.unescape());
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
@ -2176,9 +2176,9 @@ struct SimWorker : SimShared
std::map<Wire*,fstHandle> outputs;
for (auto wire : topmod->wires()) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
fstHandle id = fst->getHandle(scope + "." + wire->name.unescape());
if (id==0 && (wire->port_input || wire->port_output))
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape()));
if (wire->port_input)
if (clocks.find(wire)==clocks.end())
inputs[wire] = id;
@ -2244,13 +2244,13 @@ struct SimWorker : SimShared
}
int data_len = clk_len + inputs_len + outputs_len + 32;
f << "\n";
f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name));
f << stringf("\t%s uut(",topmod);
for(auto item=clocks.begin();item!=clocks.end();item++)
f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name), RTLIL::unescape_id(item->first->name));
f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), item->first, item->first);
for(auto &item : inputs)
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name));
f << stringf(",.%s(%s)", item.first, item.first);
for(auto &item : outputs)
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name));
f << stringf(",.%s(%s)", item.first, item.first);
f << ");\n";
f << "\n";
f << "\tinteger i;\n";

4
passes/techmap/abc.cc
View file

@ -1565,7 +1565,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
{
if (builtin_lib)
{
cell_stats[RTLIL::unescape_id(c->type)]++;
cell_stats[c->type.unescape()]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
@ -1706,7 +1706,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
}
}
else
cell_stats[RTLIL::unescape_id(c->type)]++;
cell_stats[c->type.unescape()]++;
if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn;

8
passes/techmap/extract.cc
View file

@ -626,7 +626,7 @@ struct ExtractPass : public Pass {
if (!mine_mode)
for (auto module : map->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(module->name);
std::string graph_name = "needle_" + module->name.unescape();
log("Creating needle graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports)) {
solver.addGraph(graph_name, mod_graph);
@ -637,7 +637,7 @@ struct ExtractPass : public Pass {
for (auto module : design->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name);
std::string graph_name = "haystack_" + module->name.unescape();
log("Creating haystack graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
solver.addGraph(graph_name, mod_graph);
@ -654,8 +654,8 @@ struct ExtractPass : public Pass {
for (auto needle : needle_list)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false);
log("Solving for %s in %s.\n", ("needle_" + needle->name.unescape()), haystack_it.first);
solver.solve(results, "needle_" + needle->name.unescape(), haystack_it.first, false);
}
log("Found %d matches.\n", GetSize(results));

4
passes/techmap/techmap.cc
View file

@ -616,9 +616,9 @@ struct TechmapWorker
}
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape());
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name));
parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->name.unescape());
for (auto &conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) {