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sv: complete support for implied task/function port directions

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This commit is contained in:
Zachary Snow 2020-12-31 16:14:35 -07:00
parent 48d0aeb094
commit 75abd90829
3 changed files with 39 additions and 0 deletions
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6
tests/various/func_port_implied_dir.ys Normal file
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read_verilog -sv func_port_implied_dir.sv
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert