sv: complete support for implied task/function port directions

tests/various/func_port_implied_dir.sv

@@ -0,0 +1,23 @@
+module gate(w, x, y, z);
+	function automatic integer bar(
+		integer a
+	);
+		bar = 2 ** a;
+	endfunction
+	output integer w = bar(4);
+
+	function automatic integer foo(
+		input integer a, /* implicitly input */ integer b,
+		output integer c, /* implicitly output */ integer d
+	);
+		c = 42;
+		d = 51;
+		foo = a + b + 1;
+	endfunction
+	output integer x, y, z;
+	initial x = foo(1, 2, y, z);
+endmodule
+
+module gold(w, x, y, z);
+	output integer w = 16, x = 4, y = 42, z = 51;
+endmodule

tests/various/func_port_implied_dir.ys

@@ -0,0 +1,6 @@
+read_verilog -sv func_port_implied_dir.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert