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[core] debug

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This commit is contained in:
tangxifan 2026-05-14 17:57:12 -07:00
parent c98dddfe32
commit 75a2ff3ed8
3 changed files with 8 additions and 8 deletions
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10
techlibs/rapidflex/src/clock_buffer_cmd.cc
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@ -104,9 +104,9 @@ struct InsertClockBuffer : public Pass {
void rewire_subckt(RTLIL::Module *module, RTLIL::Cell *cell, void rewire_subckt(RTLIL::Module *module, RTLIL::Cell *cell,
RTLIL::IdString id_name, std::string C_input) { RTLIL::IdString id_name, std::string C_input) {
std::string C_output = C_input + "_ckbuf"; std::string C_output = C_input + "_ckbuf";
if (!module->wire("\\" + C_output)) { // if (!module->wire("\\" + C_output)) {
auto output_wire = module->addWire("\\" + C_output, 1); // auto output_wire = module->addWire("\\" + C_output, 1);
} // }
/* connect new ckbuf to the subckt */ /* connect new ckbuf to the subckt */
cell->unsetPort(id_name); // unsetPort("C") cell->unsetPort(id_name); // unsetPort("C")
cell->setPort(id_name, module->wire("\\" + C_output)); cell->setPort(id_name, module->wire("\\" + C_output));
@ -186,7 +186,7 @@ struct InsertClockBuffer : public Pass {
representing internally generated signals. When such a signal is found, it representing internally generated signals. When such a signal is found, it
invokes rewire_subckt.*/ invokes rewire_subckt.*/
std::set<std::string> std::set<std::string>
find_internal_clk_r_signal(RTLIL::Module *module, RTLIL::Design *design, find_internal_clk_r_signal(RTLIL::Module *module,
std::map<std::string, std::string> &ckbuf_type) { std::map<std::string, std::string> &ckbuf_type) {
std::set<std::string> ckbuf_info; std::set<std::string> ckbuf_info;
/*get input ports of the top module*/ /*get input ports of the top module*/
@ -528,7 +528,7 @@ struct InsertClockBuffer : public Pass {
if (module->name == RTLIL::escape_id(top_module_name)) { if (module->name == RTLIL::escape_id(top_module_name)) {
std::map<std::string, std::string> ckbuf_type; std::map<std::string, std::string> ckbuf_type;
std::set<std::string> ckbuf_info = std::set<std::string> ckbuf_info =
find_internal_clk_r_signal(module, design, ckbuf_type); find_internal_clk_r_signal(module, ckbuf_type);
/*insert ckbuf and rewire dff */ /*insert ckbuf and rewire dff */
insert_ckbuf(module, ckbuf_info); insert_ckbuf(module, ckbuf_info);

2
techlibs/rapidflex/src/rf_dsp_mad.cc
View file

@ -4,7 +4,7 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
#include "pmgen/rf_dsp_mad.h" #include "rf_dsp_mad_pm.h"
static void create_rf_mad_dsp(rf_dsp_mad_pm &pm) { static void create_rf_mad_dsp(rf_dsp_mad_pm &pm) {
auto &st = pm.st_rf_dsp_mad; auto &st = pm.st_rf_dsp_mad;

4
techlibs/rapidflex/src/rf_new_dsp.cc
View file

@ -4,7 +4,7 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
#include "pmgen/rf_new_dsp.h" #include "rf_new_dsp_pm.h"
void swapinput(RTLIL::SigSpec &sigA, RTLIL::SigSpec &sigB) { void swapinput(RTLIL::SigSpec &sigA, RTLIL::SigSpec &sigB) {
if (GetSize(sigA) < GetSize(sigB)) { if (GetSize(sigA) < GetSize(sigB)) {
@ -438,4 +438,4 @@ struct RfNewDSP : public Pass {
} }
} RfNewDsp; } RfNewDsp;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END