mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 21:20:53 +00:00
Code Activity

Add smoke tests to tests/xilinx

Browse source
This commit is contained in:
SergeyDegtyar 2019-09-10 08:08:03 +03:00 • committed by Miodrag Milanovic
parent ca7a58bcc8
commit 757c476f62
30 changed files with 656 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

21
tests/xilinx/memory.v Normal file
View file

@ -0,0 +1,21 @@
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule