mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 15:24:57 +00:00
Code Activity

Add smoke tests to tests/xilinx

Browse source
This commit is contained in:
SergeyDegtyar 2019-09-10 08:08:03 +03:00 • committed by Miodrag Milanovic
parent ca7a58bcc8
commit 757c476f62
30 changed files with 656 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

10
tests/xilinx/logic.ys Normal file
View file

@ -0,0 +1,10 @@
read_verilog logic.v
hierarchy -top top
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D