From 7562e7304e2592ddd5a914ec723a6563c14141e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Sun, 24 Nov 2019 14:17:46 +0100
Subject: [PATCH] xilinx: Use INV instead of LUT1 when applicable
---
techlibs/xilinx/lut_map.v | 8 ++++++--
tests/arch/xilinx/adffs.ys | 4 ++--
tests/arch/xilinx/counter.ys | 4 ++--
tests/arch/xilinx/latches.ys | 4 ++--
tests/arch/xilinx/logic.ys | 4 ++--
5 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
index 13d3c3268..62d501632 100644
--- a/techlibs/xilinx/lut_map.v
+++ b/techlibs/xilinx/lut_map.v
@@ -56,8 +56,12 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]));
+ if (P_LUT == 2'b01) begin
+ INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
+ end else begin
+ LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(A[0]));
+ end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index 12c34415e..e73bfe0b9 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -20,9 +20,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
-select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
design -load read
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 57b645d19..604acdbfc 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
-select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index fe7887e8d..c87a8e38b 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -18,9 +18,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalen
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
-select -assert-none t:LDCE t:LUT1 %% t:* %D
+select -assert-none t:LDCE t:INV %% t:* %D
design -load read
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index c0f6da302..d5b5c1a37 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
-select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
+select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D