mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

Use Verific Net::{IsGnd,IsPwr} API in Verific bindings

Browse source
This commit is contained in:
Clifford Wolf 2014-03-16 16:06:03 +01:00
parent ef1795a1e8
commit 7545510edc
1 changed files with 11 additions and 27 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

38
frontends/verific/verific.cc
View file

@ -129,7 +129,7 @@ static RTLIL::SigSpec operatorOutput(Instance *inst, std::map<Net*, RTLIL::SigBi
return sig; return sig;
} }
static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, std::map<Net*, RTLIL::State> &const_map, Instance *inst) static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
{ {
if (inst->Type() == PRIM_AND) { if (inst->Type() == PRIM_AND) {
module->addAndGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput())); module->addAndGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
@ -173,12 +173,12 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == PRIM_DFFRS) if (inst->Type() == PRIM_DFFRS)
{ {
if (const_map.count(inst->GetSet()) && const_map.at(inst->GetSet()) == RTLIL::State::S0 && const_map.count(inst->GetReset()) && const_map.at(inst->GetReset()) == RTLIL::State::S0) if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
module->addDffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); module->addDffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
else if (const_map.count(inst->GetSet()) && const_map.at(inst->GetSet()) == RTLIL::State::S0) else if (inst->GetSet()->IsGnd())
module->addAdffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetReset()), module->addAdffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetReset()),
net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()), false); net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()), false);
else if (const_map.count(inst->GetReset()) && const_map.at(inst->GetReset()) == RTLIL::State::S0) else if (inst->GetReset()->IsGnd())
module->addAdffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetSet()), module->addAdffGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), net_map.at(inst->GetSet()),
net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()), true); net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()), true);
else else
@ -190,7 +190,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
return false; return false;
} }
static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, std::map<Net*, RTLIL::State> &const_map, Instance *inst) static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
{ {
if (inst->Type() == PRIM_AND) { if (inst->Type() == PRIM_AND) {
module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput())); module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
@ -248,7 +248,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
RTLIL::SigSpec out = OUT; RTLIL::SigSpec out = OUT;
if (inst->GetCout() != NULL) if (inst->GetCout() != NULL)
out.append(net_map.at(inst->GetCout())); out.append(net_map.at(inst->GetCout()));
if (const_map.count(inst->GetCin()) && const_map.at(inst->GetCin()) == RTLIL::State::S0) { if (inst->GetCin()->IsGnd()) {
module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED); module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED);
} else { } else {
RTLIL::SigSpec tmp = module->new_wire(out.width, NEW_ID); RTLIL::SigSpec tmp = module->new_wire(out.width, NEW_ID);
@ -286,7 +286,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == OPER_SHIFT_RIGHT) { if (inst->Type() == OPER_SHIFT_RIGHT) {
Net *net_cin = inst->GetCin(); Net *net_cin = inst->GetCin();
Net *net_a_msb = inst->GetInput1Bit(0); Net *net_a_msb = inst->GetInput1Bit(0);
if (const_map.count(net_cin) && const_map.at(net_cin) == RTLIL::State::S0) if (net_cin->IsGnd())
module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, false); module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, false);
else if (net_cin == net_a_msb) else if (net_cin == net_a_msb)
module->addSshr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, true); module->addSshr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, true);
@ -317,9 +317,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == OPER_LESSTHAN) { if (inst->Type() == OPER_LESSTHAN) {
Net *net_cin = inst->GetCin(); Net *net_cin = inst->GetCin();
if (const_map.count(net_cin) && const_map.at(net_cin) == RTLIL::State::S0) if (net_cin->IsGnd())
module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED); module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED);
else if (const_map.count(net_cin) && const_map.at(net_cin) == RTLIL::State::S1) else if (net_cin->IsPwr())
module->addLe(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED); module->addLe(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED);
else else
log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst->Name()); log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst->Name());
@ -407,7 +407,6 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
std::map<Net*, RTLIL::SigBit> net_map; std::map<Net*, RTLIL::SigBit> net_map;
std::map<Net*, RTLIL::State> const_map;
MapIter mi, mi2; MapIter mi, mi2;
Port *port; Port *port;
@ -546,21 +545,6 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
} }
} }
FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
{
if (inst->Type() == PRIM_PWR)
const_map[inst->GetOutput()] = RTLIL::State::S1;
if (inst->Type() == PRIM_GND)
const_map[inst->GetOutput()] = RTLIL::State::S0;
if (inst->Type() == PRIM_X)
const_map[inst->GetOutput()] = RTLIL::State::Sx;
if (inst->Type() == PRIM_Z)
const_map[inst->GetOutput()] = RTLIL::State::Sz;
}
FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst) FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
{ {
// log(" importing cell %s (%s).\n", inst->Name(), inst->View()->Owner()->Name()); // log(" importing cell %s (%s).\n", inst->Name(), inst->View()->Owner()->Name());
@ -586,13 +570,13 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
} }
if (!mode_gates) { if (!mode_gates) {
if (import_netlist_instance_cells(module, net_map, const_map, inst)) if (import_netlist_instance_cells(module, net_map, inst))
continue; continue;
if (inst->IsOperator()) if (inst->IsOperator())
log("Warning: Unsupported Verific operator: %s\n", inst->View()->Owner()->Name()); log("Warning: Unsupported Verific operator: %s\n", inst->View()->Owner()->Name());
} }
if (import_netlist_instance_gates(module, net_map, const_map, inst)) if (import_netlist_instance_gates(module, net_map, inst))
continue; continue;
if (inst->IsPrimitive()) if (inst->IsPrimitive())