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write_cxxrtl: add support for $dlatch and $dlatchsr cells.

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Also, fix codegen for $dffe and $adff.
This commit is contained in:
whitequark 2020-04-05 09:27:55 +00:00
parent 711df56ad0
commit 753e34007d
1 changed files with 16 additions and 3 deletions
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19
backends/cxxrtl/cxxrtl.cc
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@ -202,7 +202,7 @@ static bool is_sync_ff_cell(RTLIL::IdString type)
static bool is_ff_cell(RTLIL::IdString type) static bool is_ff_cell(RTLIL::IdString type)
{ {
return is_sync_ff_cell(type) || type.in( return is_sync_ff_cell(type) || type.in(
ID($adff), ID($dffsr), ID($sr)); ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
} }
static bool is_internal_cell(RTLIL::IdString type) static bool is_internal_cell(RTLIL::IdString type)
@ -786,7 +786,7 @@ struct CxxrtlWorker {
if (cell->type == ID($dffe)) { if (cell->type == ID($dffe)) {
f << indent << "if ("; f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID(EN))); dump_sigspec_rhs(cell->getPort(ID(EN)));
f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "}) {\n"; f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
inc_indent(); inc_indent();
} }
f << indent; f << indent;
@ -800,12 +800,25 @@ struct CxxrtlWorker {
} }
dec_indent(); dec_indent();
f << indent << "}\n"; f << indent << "}\n";
} else if (cell->hasPort(ID(EN))) {
// Level-sensitive logic
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID(EN)));
f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID(Q)));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID(D)));
f << ";\n";
dec_indent();
f << indent << "}\n";
} }
if (cell->hasPort(ID(ARST))) { if (cell->hasPort(ID(ARST))) {
// Asynchronous reset (entire coarse cell at once) // Asynchronous reset (entire coarse cell at once)
f << indent << "if ("; f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID(ARST))); dump_sigspec_rhs(cell->getPort(ID(ARST)));
f << " == value<1> {" << cell->getParam(ID(ARST_POLARITY)).as_bool() << "}) {\n"; f << " == value<1> {" << cell->getParam(ID(ARST_POLARITY)).as_bool() << "u}) {\n";
inc_indent(); inc_indent();
f << indent; f << indent;
dump_sigspec_lhs(cell->getPort(ID(Q))); dump_sigspec_lhs(cell->getPort(ID(Q)));