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Initialization support for all iCE40 bram modes

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This commit is contained in:
Clifford Wolf 2015-04-26 08:39:31 +02:00
parent b4d7a590e8
commit 752851954b
8 changed files with 65 additions and 28 deletions
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9
techlibs/ice40/tests/test_bram.sh
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@ -5,13 +5,8 @@ set -ex
for abits in 7 8 9 10 11 12; do
for dbits in 2 4 8 16 24 32; do
id="test_bram_${abits}_${dbits}"
if [ $((RANDOM % 2)) -eq 0 ]; then
iadr=0
idat=0
else
iadr=$((RANDOM % (1 << abits)))
idat=$((RANDOM % (1 << dbits)))
fi
iadr=$((RANDOM % (1 << abits)))
idat=$((RANDOM % ((1 << dbits) - 1) + 1))
sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram.v > ${id}.v
sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram_tb.v > ${id}_tb.v
../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v

3
techlibs/ice40/tests/test_bram.v
View file

@ -14,8 +14,7 @@ module bram #(
reg [DBITS-1:0] memory [0:2**ABITS-1];
initial begin
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
memory[INIT_ADDR] <= INIT_DATA;
end
always @(posedge clk) begin

3
techlibs/ice40/tests/test_bram_tb.v
View file

@ -64,8 +64,7 @@ module bram_tb #(
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
if (INIT_ADDR || INIT_DATA)
memory[INIT_ADDR] <= INIT_DATA;
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;