From a7e11261bd4e72eb6d33d8c8496225fae36dde85 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 21 Apr 2019 16:10:41 +0200
Subject: [PATCH 01/22] Add $specify2 and $specify3 cells to simlib

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/common/simlib.v | 147 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..f23137a06 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1271,6 +1271,152 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$specify2 (EN, SRC, DST);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_AVG = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_AVG = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specify3 (EN, SRC, DST, DAT);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter EDGE_EN = 0;
+parameter EDGE_POL = 0;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter DAT_DST_PEN = 0;
+parameter DAT_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_AVG = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_AVG = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST, DAT;
+
+localparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	// DD=0
+
+	if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	// DD=1
+
+	if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	// DD=2
+
+	if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+
+	if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$assert (A, EN);
 
 input A, EN;
@@ -1863,4 +2009,5 @@ end
 endmodule
 
 `endif
+
 // --------------------------------------------------------

From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 21 Apr 2019 21:58:57 +0200
Subject: [PATCH 02/22] Add specify parser

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_frontend.cc |  18 +-
 frontends/verilog/verilog_frontend.h  |   7 +-
 frontends/verilog/verilog_lexer.l     |   7 +-
 frontends/verilog/verilog_parser.y    | 246 +++++++++++++++++++++++---
 kernel/rtlil.cc                       |  10 ++
 5 files changed, 254 insertions(+), 34 deletions(-)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index ed6ce2ecb..8202ab9d7 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -158,6 +158,9 @@ struct VerilogFrontend : public Frontend {
 		log("        delete (* whitebox *) and (* lib_whitebox *) attributes from\n");
 		log("        all modules.\n");
 		log("\n");
+		log("    -specify\n");
+		log("        parse and import specify blocks\n");
+		log("\n");
 		log("    -noopt\n");
 		log("        don't perform basic optimizations (such as const folding) in the\n");
 		log("        high-level front-end.\n");
@@ -228,6 +231,8 @@ struct VerilogFrontend : public Frontend {
 		bool flag_nooverwrite = false;
 		bool flag_overwrite = false;
 		bool flag_defer = false;
+		bool flag_noblackbox = false;
+		bool flag_nowb = false;
 		std::map<std::string, std::string> defines_map;
 		std::list<std::string> include_dirs;
 		std::list<std::string> attributes;
@@ -237,9 +242,8 @@ struct VerilogFrontend : public Frontend {
 		formal_mode = false;
 		norestrict_mode = false;
 		assume_asserts_mode = false;
-		noblackbox_mode = false;
 		lib_mode = false;
-		nowb_mode = false;
+		specify_mode = false;
 		default_nettype_wire = true;
 
 		log_header(design, "Executing Verilog-2005 frontend.\n");
@@ -342,7 +346,7 @@ struct VerilogFrontend : public Frontend {
 				continue;
 			}
 			if (arg == "-noblackbox") {
-				noblackbox_mode = true;
+				flag_noblackbox = true;
 				continue;
 			}
 			if (arg == "-lib") {
@@ -351,7 +355,11 @@ struct VerilogFrontend : public Frontend {
 				continue;
 			}
 			if (arg == "-nowb") {
-				nowb_mode = true;
+				flag_nowb = true;
+				continue;
+			}
+			if (arg == "-specify") {
+				specify_mode = true;
 				continue;
 			}
 			if (arg == "-noopt") {
@@ -450,7 +458,7 @@ struct VerilogFrontend : public Frontend {
 			error_on_dpi_function(current_ast);
 
 		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
-				flag_nomeminit, flag_nomem2reg, flag_mem2reg, noblackbox_mode, lib_mode, nowb_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+				flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index ca40946cb..a7c9b2fe6 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -69,14 +69,11 @@ namespace VERILOG_FRONTEND
 	// running in -assert-assumes mode
 	extern bool assert_assumes_mode;
 
-	// running in -noblackbox mode
-	extern bool noblackbox_mode;
-
 	// running in -lib mode
 	extern bool lib_mode;
 
-	// running in -nowb mode
-	extern bool nowb_mode;
+	// running in -specify mode
+	extern bool specify_mode;
 
 	// lexer input stream
 	extern std::istream *lexin;
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 6ef38252a..b73ccf5c1 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -148,7 +148,7 @@ YOSYS_NAMESPACE_END
 "endfunction"  { return TOK_ENDFUNCTION; }
 "task"         { return TOK_TASK; }
 "endtask"      { return TOK_ENDTASK; }
-"specify"      { return TOK_SPECIFY; }
+"specify"      { return specify_mode ? TOK_SPECIFY : TOK_IGNORED_SPECIFY; }
 "endspecify"   { return TOK_ENDSPECIFY; }
 "specparam"    { return TOK_SPECPARAM; }
 "package"      { SV_KEYWORD(TOK_PACKAGE); }
@@ -411,6 +411,11 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 "+:" { return TOK_POS_INDEXED; }
 "-:" { return TOK_NEG_INDEXED; }
 
+[-+]?[=*]> {
+	frontend_verilog_yylval.string = new std::string(yytext);
+	return TOK_SPECIFY_OPER;
+}
+
 "/*" { BEGIN(COMMENT); }
 <COMMENT>.    /* ignore comment body */
 <COMMENT>\n   /* ignore comment body */
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 40968d17a..2e6863302 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -59,7 +59,7 @@ namespace VERILOG_FRONTEND {
 	std::vector<char> case_type_stack;
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
-	bool sv_mode, formal_mode, noblackbox_mode, lib_mode, nowb_mode;
+	bool sv_mode, formal_mode, lib_mode, specify_mode;
 	bool noassert_mode, noassume_mode, norestrict_mode;
 	bool assume_asserts_mode, assert_assumes_mode;
 	bool current_wire_rand, current_wire_const;
@@ -94,6 +94,20 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	delete al;
 }
 
+struct specify_target {
+	char polarity_op;
+	AstNode *dst, *dat;
+};
+
+struct specify_triple {
+	AstNode *t_min, *t_avg, *t_max;
+};
+
+struct specify_rise_fall {
+	specify_triple rise;
+	specify_triple fall;
+};
+
 %}
 
 %name-prefix "frontend_verilog_yy"
@@ -102,10 +116,15 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	std::string *string;
 	struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
 	std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
+	struct specify_target *specify_target_ptr;
+	struct specify_triple *specify_triple_ptr;
+	struct specify_rise_fall *specify_rise_fall_ptr;
 	bool boolean;
+	char ch;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
+%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
+%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -116,7 +135,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
-%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
+%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
+%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -130,6 +150,12 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
+%type <specify_target_ptr> specify_target
+%type <specify_triple_ptr> specify_triple
+%type <specify_rise_fall_ptr> specify_rise_fall
+%type <ast> specify_if
+%type <ch> specify_edge
+
 // operator precedence from low to high
 %left OP_LOR
 %left OP_LAND
@@ -539,7 +565,7 @@ module_body:
 
 module_body_stmt:
 	task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
-	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl;
+	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
 
 checker_decl:
 	TOK_CHECKER TOK_ID ';' {
@@ -697,15 +723,181 @@ task_func_body:
 	task_func_body behavioral_stmt |
 	/* empty */;
 
-specify_block:
-	TOK_SPECIFY specify_item_opt TOK_ENDSPECIFY |
-	TOK_SPECIFY TOK_ENDSPECIFY ;
+/*************************** specify parser ***************************/
 
-specify_item_opt:
-	specify_item_opt specify_item |
-	specify_item ;
+specify_block:
+	TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
+
+specify_item_list:
+	specify_item specify_item_list |
+	/* empty */;
 
 specify_item:
+	specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
+		AstNode *en_expr = $1;
+		char specify_edge = $3;
+		AstNode *src_expr = $4;
+		string *oper = $5;
+		specify_target *target = $6;
+		specify_rise_fall *timing = $9;
+
+		if (specify_edge != 0 && target->dat == nullptr)
+			frontend_verilog_yyerror("Found specify edge but no data spec.\n");
+
+		AstNode *cell = new AstNode(AST_CELL);
+		ast_stack.back()->children.push_back(cell);
+		cell->str = stringf("$specify$%d", autoidx++);
+		cell->children.push_back(new AstNode(AST_CELLTYPE));
+		cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
+
+		char oper_polarity = 0;
+		char oper_type = oper->at(0);
+
+		if (oper->size() == 3) {
+			oper_polarity = oper->at(0);
+			oper_type = oper->at(1);
+		}
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
+		cell->children.back()->str = "\\FULL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
+		cell->children.back()->str = "\\SRC_DST_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
+		cell->children.back()->str = "\\SRC_DST_POL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
+		cell->children.back()->str = "\\T_RISE_MIN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
+		cell->children.back()->str = "\\T_RISE_AVG";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
+		cell->children.back()->str = "\\T_RISE_MAX";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
+		cell->children.back()->str = "\\T_FALL_MIN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
+		cell->children.back()->str = "\\T_FALL_AVG";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
+		cell->children.back()->str = "\\T_FALL_MAX";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
+		cell->children.back()->str = "\\EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
+		cell->children.back()->str = "\\DST";
+
+		if (target->dat)
+		{
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
+			cell->children.back()->str = "\\EDGE_EN";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
+			cell->children.back()->str = "\\EDGE_POL";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
+			cell->children.back()->str = "\\DAT_DST_PEN";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
+			cell->children.back()->str = "\\DAT_DST_POL";
+
+			cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
+			cell->children.back()->str = "\\DAT";
+		}
+
+		delete oper;
+		delete target;
+		delete timing;
+	};
+
+specify_if:
+	TOK_IF '(' expr ')' {
+		$$ = $3;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
+specify_target:
+	expr {
+		$$ = new specify_target;
+		$$->polarity_op = 0;
+		$$->dst = $1;
+		$$->dat = nullptr;
+	} |
+	'(' expr ':' expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = 0;
+		$$->dst = $2;
+		$$->dat = $4;
+	} |
+	'(' expr TOK_NEG_INDEXED expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = '-';
+		$$->dst = $2;
+		$$->dat = $4;
+	} |
+	'(' expr TOK_POS_INDEXED expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = '+';
+		$$->dst = $2;
+		$$->dat = $4;
+	};
+
+specify_edge:
+	TOK_POSEDGE { $$ = 'p'; } |
+	TOK_NEGEDGE { $$ = 'n'; } |
+	{ $$ = 0; };
+
+specify_rise_fall:
+	specify_triple {
+		$$ = new specify_rise_fall;
+		$$->rise = *$1;
+		$$->fall.t_min = $1->t_min->clone();
+		$$->fall.t_avg = $1->t_avg->clone();
+		$$->fall.t_max = $1->t_max->clone();
+		delete $1;
+	} |
+	'(' specify_triple ',' specify_triple ')' {
+		$$ = new specify_rise_fall;
+		$$->rise = *$2;
+		$$->fall = *$4;
+		delete $2;
+		delete $4;
+	};
+
+specify_triple:
+	expr {
+		$$ = new specify_triple;
+		$$->t_min = $1;
+		$$->t_avg = $1->clone();
+		$$->t_max = $1->clone();
+	} |
+	expr ':' expr ':' expr {
+		$$ = new specify_triple;
+		$$->t_min = $1;
+		$$->t_avg = $3;
+		$$->t_max = $5;
+	};
+
+/******************** ignored specify parser **************************/
+
+ignored_specify_block:
+	TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
+	TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
+
+ignored_specify_item_opt:
+	ignored_specify_item_opt ignored_specify_item |
+	ignored_specify_item ;
+
+ignored_specify_item:
 	specparam_declaration
 	// | pulsestyle_declaration
 	// | showcancelled_declaration
@@ -721,13 +913,13 @@ specparam_declaration:
 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
 // exxxxtending this for SV specparam would change this anyhow
 specparam_range:
-	'[' constant_expression ':' constant_expression ']' ;
+	'[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
 
 list_of_specparam_assignments:
 	specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
 
 specparam_assignment:
-	TOK_ID '=' constant_mintypmax_expression ;
+	ignspec_id '=' constant_mintypmax_expression ;
 
 /*
 pulsestyle_declaration :
@@ -802,19 +994,19 @@ opt_polarity_operator :
 
 // Good enough for the time being
 specify_input_terminal_descriptor :
-	TOK_ID ;
+	ignspec_id ;
 
 // Good enough for the time being
 specify_output_terminal_descriptor :
-	TOK_ID ;
+	ignspec_id ;
 
 system_timing_declaration :
-	TOK_ID '(' system_timing_args ')' ';' ;
+	ignspec_id '(' system_timing_args ')' ';' ;
 
 system_timing_arg :
-	TOK_POSEDGE TOK_ID |
-	TOK_NEGEDGE TOK_ID |
-	expr ;
+	TOK_POSEDGE ignspec_id |
+	TOK_NEGEDGE ignspec_id |
+	ignspec_expr ;
 
 system_timing_args :
 	system_timing_arg |
@@ -871,19 +1063,27 @@ tzx_path_delay_expression :
 */
 
 path_delay_expression :
-	constant_expression;
+	ignspec_constant_expression;
 
 constant_mintypmax_expression :
-	constant_expression
-	| constant_expression ':' constant_expression ':' constant_expression
+	ignspec_constant_expression
+	| ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
 	;
 
 // for the time being this is OK, but we may write our own expr here.
 // as I'm not sure it is legal to use a full expr here (probably not)
 // On the other hand, other rules requiring constant expressions also use 'expr'
 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
-constant_expression:
-	expr ;
+ignspec_constant_expression:
+	expr { delete $1; };
+
+ignspec_expr:
+	expr { delete $1; };
+
+ignspec_id:
+	TOK_ID { delete $1; };
+
+/**********************************************************************/
 
 param_signed:
 	TOK_SIGNED {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7e1159cac..7d5334eb1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1194,6 +1194,16 @@ namespace {
 				return;
 			}
 
+			if (cell->type == "$specify2") {
+				// FIXME
+				return;
+			}
+
+			if (cell->type == "$specify3") {
+				// FIXME
+				return;
+			}
+
 			if (cell->type == "$_BUF_")    { check_gate("AY"); return; }
 			if (cell->type == "$_NOT_")    { check_gate("AY"); return; }
 			if (cell->type == "$_AND_")    { check_gate("ABY"); return; }

From 41b843c27b486ef4b3c0044fbb00b161faaf89d9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 21 Apr 2019 22:58:51 +0200
Subject: [PATCH 03/22] Un-break default specify parser

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index b73ccf5c1..f49f9d3a2 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -412,6 +412,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 "-:" { return TOK_NEG_INDEXED; }
 
 [-+]?[=*]> {
+	if (!specify_mode) REJECT;
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_SPECIFY_OPER;
 }

From b232e027bf18bd37206c15209e23d2f8f7b2a17d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 02:33:12 +0200
Subject: [PATCH 04/22] Checking and fixing specify cells in genRTLIL

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b3a2a84be..b2a22b49a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1521,9 +1521,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
+			if (cell->type.in("$specify2", "$specify3")) {
+				int src_width = GetSize(cell->getPort("\\SRC"));
+				int dst_width = GetSize(cell->getPort("\\DST"));
+				bool full = cell->getParam("\\FULL").as_bool();
+				if (!full && src_width != dst_width)
+					log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
+				if (cell->type == "$specify3") {
+					int dat_width = GetSize(cell->getPort("\\DAT"));
+					if (dat_width != dst_width)
+						log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
+				}
+				cell->setParam("\\SRC_WIDTH", Const(src_width));
+				cell->setParam("\\DST_WIDTH", Const(dst_width));
+			}
 		}
 		break;
 

From e1d73e03d38e9408cc7bce685645bb170ca5a6b8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:26:20 +0200
Subject: [PATCH 05/22] Add InternalCellChecker support for $specify2 and
 $specify3

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/rtlil.cc | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7d5334eb1..9e06b8323 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1194,13 +1194,27 @@ namespace {
 				return;
 			}
 
-			if (cell->type == "$specify2") {
-				// FIXME
-				return;
-			}
-
-			if (cell->type == "$specify3") {
-				// FIXME
+			if (cell->type.in("$specify2", "$specify3")) {
+				param_bool("\\FULL");
+				param_bool("\\SRC_DST_PEN");
+				param_bool("\\SRC_DST_POL");
+				param("\\T_RISE_MIN");
+				param("\\T_RISE_AVG");
+				param("\\T_RISE_MAX");
+				param("\\T_FALL_MIN");
+				param("\\T_FALL_AVG");
+				param("\\T_FALL_MAX");
+				port("\\EN", 1);
+				port("\\SRC", param("\\SRC_WIDTH"));
+				port("\\DST", param("\\DST_WIDTH"));
+				if (cell->type == "$specify3") {
+					param_bool("\\EDGE_EN");
+					param_bool("\\EDGE_POL");
+					param_bool("\\DAT_DST_PEN");
+					param_bool("\\DAT_DST_POL");
+					port("\\DAT", param("\\DST_WIDTH"));
+				}
+				check_expected();
 				return;
 			}
 

From aec2475a9d7a2a903d5015840a3320ce2cedf5cd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:29:59 +0200
Subject: [PATCH 06/22] Add CellTypes support for $specify2 and $specify3

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/celltypes.h         | 3 +++
 manual/CHAPTER_CellLib.tex | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 0da78c313..f8c73ed83 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -85,6 +85,7 @@ struct CellTypes
 		setup_internals_eval();
 
 		IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y";
+		IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT";
 
 		setup_type("$tribuf", {A, EN}, {Y}, true);
 
@@ -99,6 +100,8 @@ struct CellTypes
 		setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
 		setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
 		setup_type("$equiv", {A, B}, {Y}, true);
+		setup_type("$specify2", {EN, SRC, DST}, pool<RTLIL::IdString>(), true);
+		setup_type("$specify3", {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true);
 	}
 
 	void setup_internals_eval()
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e64919182..96a309552 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -465,6 +465,10 @@ Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}
 {\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$specify2} and {\tt \$specify3} cells.
+\end{fixme}
+
 \begin{fixme}
 Add information about {\tt \$slice} and {\tt \$concat} cells.
 \end{fixme}

From 0bf9d0087c43f9db3d56cb2bed17268def21eb67 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:35:14 +0200
Subject: [PATCH 07/22] Add support for $assert/$assume/$cover to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9967482d6..1c65e79b7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1242,6 +1242,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type.in("$assert", "$assume", "$cover"))
+	{
+		f << stringf("%s" "always @* if (", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(") %s(", cell->type.c_str()+1);
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(");\n");
+		return true;
+	}
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
 

From 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:49:55 +0200
Subject: [PATCH 08/22] Add $specify2/$specify3 support to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 1c65e79b7..6bb08fdb2 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1252,6 +1252,53 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type.in("$specify2", "$specify3"))
+	{
+		f << stringf("%s" "specify\n%s  ", indent.c_str(), indent.c_str());
+
+		SigSpec en = cell->getPort("\\EN");
+		if (en != State::S1) {
+			f << stringf("if (");
+			dump_sigspec(f, cell->getPort("\\EN"));
+			f << stringf(") ");
+		}
+
+		f << "(";
+		if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool())
+			f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge ");
+
+		dump_sigspec(f, cell->getPort("\\SRC"));
+
+		f << " ";
+		if (cell->getParam("\\SRC_DST_PEN").as_bool())
+			f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-");
+		f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> ");
+
+		if (cell->type == "$specify3") {
+			f << "(";
+			dump_sigspec(f, cell->getPort("\\DST"));
+			f << " ";
+			if (cell->getParam("\\DAT_DST_PEN").as_bool())
+				f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-");
+			f << ": ";
+			dump_sigspec(f, cell->getPort("\\DAT"));
+			f << ")";
+		} else {
+			dump_sigspec(f, cell->getPort("\\DST"));
+		}
+
+		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
+				cell->getParam("\\T_RISE_MIN").as_int(),
+				cell->getParam("\\T_RISE_AVG").as_int(),
+				cell->getParam("\\T_RISE_MAX").as_int(),
+				cell->getParam("\\T_FALL_MIN").as_int(),
+				cell->getParam("\\T_FALL_AVG").as_int(),
+				cell->getParam("\\T_FALL_MAX").as_int());
+
+		f << stringf("%s" "endspecify\n", indent.c_str());
+		return true;
+	}
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
 

From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:52:47 +0200
Subject: [PATCH 09/22] Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better
 match verilog std nomenclature

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc |   4 +-
 frontends/verilog/verilog_parser.y  |   4 +-
 kernel/rtlil.cc                     |   4 +-
 techlibs/common/simlib.v            | 128 ++++++++++++++--------------
 4 files changed, 70 insertions(+), 70 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6bb08fdb2..93eaa8feb 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1289,10 +1289,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
 				cell->getParam("\\T_RISE_MIN").as_int(),
-				cell->getParam("\\T_RISE_AVG").as_int(),
+				cell->getParam("\\T_RISE_TYP").as_int(),
 				cell->getParam("\\T_RISE_MAX").as_int(),
 				cell->getParam("\\T_FALL_MIN").as_int(),
-				cell->getParam("\\T_FALL_AVG").as_int(),
+				cell->getParam("\\T_FALL_TYP").as_int(),
 				cell->getParam("\\T_FALL_MAX").as_int());
 
 		f << stringf("%s" "endspecify\n", indent.c_str());
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2e6863302..218d6f738 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -771,7 +771,7 @@ specify_item:
 		cell->children.back()->str = "\\T_RISE_MIN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
-		cell->children.back()->str = "\\T_RISE_AVG";
+		cell->children.back()->str = "\\T_RISE_TYP";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
 		cell->children.back()->str = "\\T_RISE_MAX";
@@ -780,7 +780,7 @@ specify_item:
 		cell->children.back()->str = "\\T_FALL_MIN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
-		cell->children.back()->str = "\\T_FALL_AVG";
+		cell->children.back()->str = "\\T_FALL_TYP";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
 		cell->children.back()->str = "\\T_FALL_MAX";
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9e06b8323..4522b0a08 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1199,10 +1199,10 @@ namespace {
 				param_bool("\\SRC_DST_PEN");
 				param_bool("\\SRC_DST_POL");
 				param("\\T_RISE_MIN");
-				param("\\T_RISE_AVG");
+				param("\\T_RISE_TYP");
 				param("\\T_RISE_MAX");
 				param("\\T_FALL_MIN");
-				param("\\T_FALL_AVG");
+				param("\\T_FALL_TYP");
 				param("\\T_FALL_MAX");
 				port("\\EN", 1);
 				port("\\SRC", param("\\SRC_WIDTH"));
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f23137a06..f9e45df67 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1281,11 +1281,11 @@ parameter SRC_DST_PEN = 0;
 parameter SRC_DST_POL = 0;
 
 parameter T_RISE_MIN = 0;
-parameter T_RISE_AVG = 0;
+parameter T_RISE_TYP = 0;
 parameter T_RISE_MAX = 0;
 
 parameter T_FALL_MIN = 0;
-parameter T_FALL_AVG = 0;
+parameter T_FALL_TYP = 0;
 parameter T_FALL_MAX = 0;
 
 input EN;
@@ -1296,12 +1296,12 @@ localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
 
 `ifdef SIMLIB_SPECIFY
 specify
-	if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 endspecify
 `endif
 
@@ -1325,11 +1325,11 @@ parameter DAT_DST_PEN = 0;
 parameter DAT_DST_POL = 0;
 
 parameter T_RISE_MIN = 0;
-parameter T_RISE_AVG = 0;
+parameter T_RISE_TYP = 0;
 parameter T_RISE_MAX = 0;
 
 parameter T_FALL_MIN = 0;
-parameter T_FALL_AVG = 0;
+parameter T_FALL_TYP = 0;
 parameter T_FALL_MAX = 0;
 
 input EN;
@@ -1344,72 +1344,72 @@ localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
 specify
 	// DD=0
 
-	if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
 	// DD=1
 
-	if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
 	// DD=2
 
-	if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 
-	if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
-	if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_AVG:T_RISE_MAX, T_FALL_MIN:T_FALL_AVG:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
 endspecify
 `endif
 

From 012c6af088a22c035ce1244954b6625188478480 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:59:49 +0200
Subject: [PATCH 10/22] Allow $specify[23] cells in blackbox modules

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 9f88b08c1..6b3604ee5 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -951,6 +951,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 					continue;
 				if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
 					continue;
+				if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
+						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3"))
+					continue;
 				blackbox_module = false;
 				break;
 			}
@@ -1035,6 +1038,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 					child->delete_children();
 					child->children.push_back(AstNode::mkconst_int(0, false, 0));
 					new_children.push_back(child);
+				} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
+						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) {
+					new_children.push_back(child);
 				} else {
 					delete child;
 				}

From 634482380cfe5d6a1c801af0ce04e8048c5c9baf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 10:03:18 +0200
Subject: [PATCH 11/22] Preserve $specify[23] cells

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/opt_clean.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c38e9df5e..3f38dd580 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -64,7 +64,7 @@ struct keep_cache_t
 
 	bool query(Cell *cell)
 	{
-		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover"))
+		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3"))
 			return true;
 
 		if (cell->has_keep_attr())

From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 15:46:40 +0200
Subject: [PATCH 12/22] Add $specrule cells for $setup/$hold/$skew specify
 rules

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.cc               |  4 +-
 frontends/ast/genrtlil.cc          |  6 +++
 frontends/verilog/verilog_lexer.l  | 11 +++++
 frontends/verilog/verilog_parser.y | 69 +++++++++++++++++++++++++++++-
 kernel/celltypes.h                 |  2 +
 kernel/rtlil.cc                    | 15 +++++++
 manual/CHAPTER_CellLib.tex         |  2 +-
 passes/opt/opt_clean.cc            |  2 +-
 techlibs/common/simlib.v           | 28 ++++++++++++
 9 files changed, 133 insertions(+), 6 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 6b3604ee5..5623541b2 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -952,7 +952,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 				if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
 					continue;
 				if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
-						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3"))
+						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule"))
 					continue;
 				blackbox_module = false;
 				break;
@@ -1039,7 +1039,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 					child->children.push_back(AstNode::mkconst_int(0, false, 0));
 					new_children.push_back(child);
 				} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
-						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) {
+						(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {
 					new_children.push_back(child);
 				} else {
 					delete child;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b2a22b49a..48bd466e6 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1538,6 +1538,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->setParam("\\SRC_WIDTH", Const(src_width));
 				cell->setParam("\\DST_WIDTH", Const(dst_width));
 			}
+			if (cell->type == "$specrule") {
+				int src_width = GetSize(cell->getPort("\\SRC"));
+				int dst_width = GetSize(cell->getPort("\\DST"));
+				cell->setParam("\\SRC_WIDTH", Const(src_width));
+				cell->setParam("\\DST_WIDTH", Const(dst_width));
+			}
 		}
 		break;
 
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index f49f9d3a2..cd96236a1 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -301,6 +301,12 @@ supply1 { return TOK_SUPPLY1; }
 	return TOK_ID;
 }
 
+"$"(setup|hold|skew) {
+	if (!specify_mode) REJECT;
+	frontend_verilog_yylval.string = new std::string(yytext);
+	return TOK_ID;
+}
+
 "$signed"   { return TOK_TO_SIGNED; }
 "$unsigned" { return TOK_TO_UNSIGNED; }
 
@@ -417,6 +423,11 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 	return TOK_SPECIFY_OPER;
 }
 
+"&&&" {
+	if (!specify_mode) REJECT;
+	return TOK_SPECIFY_AND;
+}
+
 "/*" { BEGIN(COMMENT); }
 <COMMENT>.    /* ignore comment body */
 <COMMENT>\n   /* ignore comment body */
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 218d6f738..0a41ba581 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -136,7 +136,7 @@ struct specify_rise_fall {
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
-%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
+%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -153,7 +153,7 @@ struct specify_rise_fall {
 %type <specify_target_ptr> specify_target
 %type <specify_triple_ptr> specify_triple
 %type <specify_rise_fall_ptr> specify_rise_fall
-%type <ast> specify_if
+%type <ast> specify_if specify_condition
 %type <ch> specify_edge
 
 // operator precedence from low to high
@@ -815,6 +815,63 @@ specify_item:
 		delete oper;
 		delete target;
 		delete timing;
+	} |
+	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
+		bool limit_gt = false;
+		if (*$1 == "$setup" || *$1 == "$hold")
+			limit_gt = true;
+		else if (*$1 == "$skew")
+			limit_gt = false;
+		else
+			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
+
+		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
+		AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
+		AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
+
+		AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
+		AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
+		AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
+
+		AstNode *limit = $11;
+
+		AstNode *cell = new AstNode(AST_CELL);
+		ast_stack.back()->children.push_back(cell);
+		cell->str = stringf("$specify$%d", autoidx++);
+		cell->children.push_back(new AstNode(AST_CELLTYPE));
+		cell->children.back()->str = "$specrule";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
+		cell->children.back()->str = "\\SRC_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
+		cell->children.back()->str = "\\SRC_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, src_pol));
+		cell->children.back()->str = "\\SRC_POL";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
+		cell->children.back()->str = "\\DST_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
+		cell->children.back()->str = "\\DST";
+
+		cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
+		cell->children.back()->str = "\\DST_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
+		cell->children.back()->str = "\\DST_POL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(limit_gt, false, 1)));
+		cell->children.back()->str = "\\LIMIT_GT";
+
+		cell->children.push_back(new AstNode(AST_PARASET, limit));
+		cell->children.back()->str = "\\T_LIMIT";
+
+		delete $1;
 	};
 
 specify_if:
@@ -825,6 +882,14 @@ specify_if:
 		$$ = nullptr;
 	};
 
+specify_condition:
+	TOK_SPECIFY_AND expr {
+		$$ = $2;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
 specify_target:
 	expr {
 		$$ = new specify_target;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index f8c73ed83..4e91eddda 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -86,6 +86,7 @@ struct CellTypes
 
 		IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y";
 		IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT";
+		IdString EN_SRC = "\\EN_SRC", EN_DST = "\\EN_DST";
 
 		setup_type("$tribuf", {A, EN}, {Y}, true);
 
@@ -102,6 +103,7 @@ struct CellTypes
 		setup_type("$equiv", {A, B}, {Y}, true);
 		setup_type("$specify2", {EN, SRC, DST}, pool<RTLIL::IdString>(), true);
 		setup_type("$specify3", {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true);
+		setup_type("$specrule", {EN_SRC, EN_DST, SRC, DST}, pool<RTLIL::IdString>(), true);
 	}
 
 	void setup_internals_eval()
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4522b0a08..dae3698a9 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1218,6 +1218,21 @@ namespace {
 				return;
 			}
 
+			if (cell->type == "$specrule") {
+				param_bool("\\SRC_PEN");
+				param_bool("\\SRC_POL");
+				param_bool("\\DST_PEN");
+				param_bool("\\DST_POL");
+				param_bool("\\LIMIT_GT");
+				param("\\T_LIMIT");
+				port("\\SRC_EN", 1);
+				port("\\DST_EN", 1);
+				port("\\SRC", param("\\SRC_WIDTH"));
+				port("\\DST", param("\\DST_WIDTH"));
+				check_expected();
+				return;
+			}
+
 			if (cell->type == "$_BUF_")    { check_gate("AY"); return; }
 			if (cell->type == "$_NOT_")    { check_gate("AY"); return; }
 			if (cell->type == "$_AND_")    { check_gate("ABY"); return; }
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 96a309552..cb1bcf1be 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -466,7 +466,7 @@ Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}
 \end{fixme}
 
 \begin{fixme}
-Add information about {\tt \$specify2} and {\tt \$specify3} cells.
+Add information about {\tt \$specify2}, {\tt \$specify3}, and {\tt \$specrule} cells.
 \end{fixme}
 
 \begin{fixme}
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 3f38dd580..3e131d2af 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -64,7 +64,7 @@ struct keep_cache_t
 
 	bool query(Cell *cell)
 	{
-		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3"))
+		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3", "$specrule"))
 			return true;
 
 		if (cell->has_keep_attr())
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f9e45df67..facecd9a4 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1417,6 +1417,34 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$specrule (EN_SRC, EN_DST, SRC, DST);
+
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_PEN = 0;
+parameter SRC_POL = 0;
+
+parameter DST_PEN = 0;
+parameter DST_POL = 0;
+
+parameter LIMIT_GT = 0;
+parameter T_LIMIT = 0;
+
+input EN_SRC, EN_DST;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	// TBD
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$assert (A, EN);
 
 input A, EN;

From 4575e4ad86494e99dd05200f7242dfa632053c78 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 22:18:04 +0200
Subject: [PATCH 13/22] Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 38 ++++++++++++++----------------
 kernel/rtlil.cc                    |  3 ++-
 techlibs/common/simlib.v           |  7 +++---
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0a41ba581..13ff1d38b 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -817,12 +817,7 @@ specify_item:
 		delete timing;
 	} |
 	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
-		bool limit_gt = false;
-		if (*$1 == "$setup" || *$1 == "$hold")
-			limit_gt = true;
-		else if (*$1 == "$skew")
-			limit_gt = false;
-		else
+		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$skew")
 			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
 
 		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
@@ -841,11 +836,14 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_CELLTYPE));
 		cell->children.back()->str = "$specrule";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
-		cell->children.back()->str = "\\SRC_EN";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$skew", false, 1)));
+		cell->children.back()->str = "\\SKEW";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
-		cell->children.back()->str = "\\SRC";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$hold", false, 1)));
+		cell->children.back()->str = "\\HOLD";
+
+		cell->children.push_back(new AstNode(AST_PARASET, limit));
+		cell->children.back()->str = "\\T_LIMIT";
 
 		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
 		cell->children.back()->str = "\\SRC_PEN";
@@ -853,23 +851,23 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_PARASET, src_pol));
 		cell->children.back()->str = "\\SRC_POL";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
-		cell->children.back()->str = "\\DST_EN";
-
-		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
-		cell->children.back()->str = "\\DST";
-
 		cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
 		cell->children.back()->str = "\\DST_PEN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
 		cell->children.back()->str = "\\DST_POL";
 
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(limit_gt, false, 1)));
-		cell->children.back()->str = "\\LIMIT_GT";
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
+		cell->children.back()->str = "\\SRC_EN";
 
-		cell->children.push_back(new AstNode(AST_PARASET, limit));
-		cell->children.back()->str = "\\T_LIMIT";
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
+		cell->children.back()->str = "\\DST_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
+		cell->children.back()->str = "\\DST";
 
 		delete $1;
 	};
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index dae3698a9..3dd18c296 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1223,7 +1223,8 @@ namespace {
 				param_bool("\\SRC_POL");
 				param_bool("\\DST_PEN");
 				param_bool("\\DST_POL");
-				param_bool("\\LIMIT_GT");
+				param_bool("\\SKEW");
+				param_bool("\\HOLD");
 				param("\\T_LIMIT");
 				port("\\SRC_EN", 1);
 				port("\\DST_EN", 1);
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index facecd9a4..965242cdc 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1419,6 +1419,10 @@ endmodule
 
 module \$specrule (EN_SRC, EN_DST, SRC, DST);
 
+parameter SKEW = 0;
+parameter HOLD = 0;
+parameter T_LIMIT = 0;
+
 parameter SRC_WIDTH = 1;
 parameter DST_WIDTH = 1;
 
@@ -1428,9 +1432,6 @@ parameter SRC_POL = 0;
 parameter DST_PEN = 0;
 parameter DST_POL = 0;
 
-parameter LIMIT_GT = 0;
-parameter T_LIMIT = 0;
-
 input EN_SRC, EN_DST;
 input [SRC_WIDTH-1:0] SRC;
 input [DST_WIDTH-1:0] DST;

From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 22:57:10 +0200
Subject: [PATCH 14/22] Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l  |  2 +-
 frontends/verilog/verilog_parser.y | 26 ++++++++++++++++++--------
 kernel/rtlil.cc                    |  4 ++--
 techlibs/common/simlib.v           |  4 ++--
 4 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index cd96236a1..1a818a2ce 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -301,7 +301,7 @@ supply1 { return TOK_SUPPLY1; }
 	return TOK_ID;
 }
 
-"$"(setup|hold|skew) {
+"$"(setup|hold|setuphold|removal|recovery|recrem|skew|timeskew|fullskew|nochange) {
 	if (!specify_mode) REJECT;
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_ID;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 13ff1d38b..351f38101 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -153,7 +153,7 @@ struct specify_rise_fall {
 %type <specify_target_ptr> specify_target
 %type <specify_triple_ptr> specify_triple
 %type <specify_rise_fall_ptr> specify_rise_fall
-%type <ast> specify_if specify_condition
+%type <ast> specify_if specify_condition specify_opt_arg
 %type <ch> specify_edge
 
 // operator precedence from low to high
@@ -816,8 +816,9 @@ specify_item:
 		delete target;
 		delete timing;
 	} |
-	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
-		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$skew")
+	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr specify_opt_arg ')' ';' {
+		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
+				*$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
 			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
 
 		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
@@ -829,6 +830,7 @@ specify_item:
 		AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
 
 		AstNode *limit = $11;
+		AstNode *limit2 = $12;
 
 		AstNode *cell = new AstNode(AST_CELL);
 		ast_stack.back()->children.push_back(cell);
@@ -836,15 +838,15 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_CELLTYPE));
 		cell->children.back()->str = "$specrule";
 
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$skew", false, 1)));
-		cell->children.back()->str = "\\SKEW";
-
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$hold", false, 1)));
-		cell->children.back()->str = "\\HOLD";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
+		cell->children.back()->str = "\\TYPE";
 
 		cell->children.push_back(new AstNode(AST_PARASET, limit));
 		cell->children.back()->str = "\\T_LIMIT";
 
+		cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2 : AstNode::mkconst_int(0, true)));
+		cell->children.back()->str = "\\T_LIMIT2";
+
 		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
 		cell->children.back()->str = "\\SRC_PEN";
 
@@ -872,6 +874,14 @@ specify_item:
 		delete $1;
 	};
 
+specify_opt_arg:
+	',' expr {
+		$$ = $2;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
 specify_if:
 	TOK_IF '(' expr ')' {
 		$$ = $3;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 3dd18c296..040644c47 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1219,13 +1219,13 @@ namespace {
 			}
 
 			if (cell->type == "$specrule") {
+				param("\\TYPE");
 				param_bool("\\SRC_PEN");
 				param_bool("\\SRC_POL");
 				param_bool("\\DST_PEN");
 				param_bool("\\DST_POL");
-				param_bool("\\SKEW");
-				param_bool("\\HOLD");
 				param("\\T_LIMIT");
+				param("\\T_LIMIT2");
 				port("\\SRC_EN", 1);
 				port("\\DST_EN", 1);
 				port("\\SRC", param("\\SRC_WIDTH"));
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 965242cdc..a424d3089 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1419,9 +1419,9 @@ endmodule
 
 module \$specrule (EN_SRC, EN_DST, SRC, DST);
 
-parameter SKEW = 0;
-parameter HOLD = 0;
+parameter TYPE = "";
 parameter T_LIMIT = 0;
+parameter T_LIMIT2 = 0;
 
 parameter SRC_WIDTH = 1;
 parameter DST_WIDTH = 1;

From 67005633e246e47683b11e13f08afb788bc9de02 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 23:01:38 +0200
Subject: [PATCH 15/22] Add specify support to README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 README.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/README.md b/README.md
index 913777f2e..d21d60c97 100644
--- a/README.md
+++ b/README.md
@@ -424,6 +424,11 @@ Verilog Attributes and non-standard features
   in an unconditional context (only if/case statements on parameters
   and constant values). The intended use for this is synthesis-time DRC.
 
+- There is limited support for converting specify .. endspecify statements to
+  special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
+  blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
+  functionality. (By default specify .. endspecify blocks are ignored.)
+
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================

From 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:35:26 -0700
Subject: [PATCH 16/22] Add quick-and-dirty specify tests

---
 tests/various/specify.v  | 28 ++++++++++++++++++++++++++++
 tests/various/specify.ys | 25 +++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 tests/various/specify.v
 create mode 100644 tests/various/specify.ys

diff --git a/tests/various/specify.v b/tests/various/specify.v
new file mode 100644
index 000000000..aea0d0fc5
--- /dev/null
+++ b/tests/various/specify.v
@@ -0,0 +1,28 @@
+module test (
+	input EN, CLK,
+	input [3:0] D,
+	output reg [3:0] Q
+);
+	always @(posedge CLK)
+		if (EN) Q <= D;
+
+	specify
+		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+		$setup(D, posedge CLK &&& EN, 5);
+		$hold(posedge CLK, D &&& EN, 6);
+	endspecify
+endmodule
+
+module test2 (
+    input A, B,
+	output Q
+);
+    xor (Q, A, B);
+	specify
+		//specparam T_rise = 1;
+        //specparam T_fall = 2;
+        `define T_rise 1
+        `define T_fall 2
+        (A => Q) = (`T_rise,`T_fall);
+	endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
new file mode 100644
index 000000000..c4e901705
--- /dev/null
+++ b/tests/various/specify.ys
@@ -0,0 +1,25 @@
+read_verilog -specify specify.v
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+write_verilog specify.out
+design -stash gold
+
+read_verilog -specify specify.out
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+design -stash gate
+
+# TODO: How to check $specify and $specrule-s are equivalent?

From bfb8b3018bbe2017ab35fbdc21813f69c56514bb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:42:02 -0700
Subject: [PATCH 17/22] Fix spacing

---
 tests/various/specify.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/various/specify.v b/tests/various/specify.v
index aea0d0fc5..68d3e33fc 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -14,15 +14,15 @@ module test (
 endmodule
 
 module test2 (
-    input A, B,
+	input A, B,
 	output Q
 );
-    xor (Q, A, B);
+	xor (Q, A, B);
 	specify
 		//specparam T_rise = 1;
-        //specparam T_fall = 2;
-        `define T_rise 1
-        `define T_fall 2
-        (A => Q) = (`T_rise,`T_fall);
+		//specparam T_fall = 2;
+		`define T_rise 1
+		`define T_fall 2
+		(A => Q) = (`T_rise,`T_fall);
 	endspecify
 endmodule

From 554c58715aa4f8f5ed9fb4293946ac420d3f67a2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:54:25 -0700
Subject: [PATCH 18/22] More testing

---
 tests/various/specify.v  | 2 ++
 tests/various/specify.ys | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 68d3e33fc..afc421da8 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -24,5 +24,7 @@ module test2 (
 		`define T_rise 1
 		`define T_fall 2
 		(A => Q) = (`T_rise,`T_fall);
+		//(B => Q) = (`T_rise+`T_fall)/2.0;
+		(B => Q) = 1.5;
 	endspecify
 endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index c4e901705..87d98e0a0 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -5,7 +5,7 @@ select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
 select t:$specrule -assert-count 2
 cd test2
-select t:$specify2 -assert-count 1
+select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
 write_verilog specify.out
@@ -17,9 +17,10 @@ select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
 select t:$specrule -assert-count 2
 cd test2
-select t:$specify2 -assert-count 1
+select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
 design -stash gate
 
 # TODO: How to check $specify and $specrule-s are equivalent?
+#       Otherwise, need more select statements to check parameter values are as expected?

From e2fb8ebe86f49523168c413c734ce4690d740351 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 08:01:39 +0200
Subject: [PATCH 19/22] Update README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 README.md | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/README.md b/README.md
index d21d60c97..195329a37 100644
--- a/README.md
+++ b/README.md
@@ -259,11 +259,7 @@ for them:
 
 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
 
-- The ``config`` keyword and library map files
-
-- The ``disable``, ``primitive`` and ``specify`` statements
-
-- Latched logic (is synthesized as logic with feedback loops)
+- The ``config`` and ``disable`` keywords and library map files
 
 
 Verilog Attributes and non-standard features

From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 08:46:24 +0200
Subject: [PATCH 20/22] Improve write_verilog specify support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 86 ++++++++++++++++++++++++-----
 frontends/ast/genrtlil.cc           |  3 +
 kernel/rtlil.h                      |  2 +-
 3 files changed, 75 insertions(+), 16 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 93eaa8feb..9fd4ccbc8 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -183,8 +183,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	return true;
 }
 
-void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false, bool escape_comment = false)
+void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool escape_comment = false)
 {
+	bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 	if (width < 0)
 		width = data.bits.size() - offset;
 	if (width == 0) {
@@ -275,7 +276,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			}
 		}
 	} else {
-		f << stringf("\"");
+		if ((data.flags & RTLIL::CONST_FLAG_REAL) == 0)
+			f << stringf("\"");
 		std::string str = data.decode_string();
 		for (size_t i = 0; i < str.size(); i++) {
 			if (str[i] == '\n')
@@ -293,7 +295,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			else
 				f << str[i];
 		}
-		f << stringf("\"");
+		if ((data.flags & RTLIL::CONST_FLAG_REAL) == 0)
+			f << stringf("\"");
 	}
 }
 
@@ -373,7 +376,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, false, attr2comment);
+			dump_const(f, it->second, -1, 0, false, attr2comment);
 		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
 	}
 }
@@ -1287,13 +1290,68 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_sigspec(f, cell->getPort("\\DST"));
 		}
 
-		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
-				cell->getParam("\\T_RISE_MIN").as_int(),
-				cell->getParam("\\T_RISE_TYP").as_int(),
-				cell->getParam("\\T_RISE_MAX").as_int(),
-				cell->getParam("\\T_FALL_MIN").as_int(),
-				cell->getParam("\\T_FALL_TYP").as_int(),
-				cell->getParam("\\T_FALL_MAX").as_int());
+		bool bak_decimal = decimal;
+		decimal = 1;
+
+		f << ") = (";
+		dump_const(f, cell->getParam("\\T_RISE_MIN"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_RISE_TYP"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_RISE_MAX"));
+		f << ", ";
+		dump_const(f, cell->getParam("\\T_FALL_MIN"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_FALL_TYP"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_FALL_MAX"));
+		f << ");\n";
+
+		decimal = bak_decimal;
+
+		f << stringf("%s" "endspecify\n", indent.c_str());
+		return true;
+	}
+
+	if (cell->type == "$specrule")
+	{
+		f << stringf("%s" "specify\n%s  ", indent.c_str(), indent.c_str());
+
+		string spec_type = cell->getParam("\\TYPE").decode_string();
+		f << stringf("%s(", spec_type.c_str());
+
+		if (cell->getParam("\\SRC_PEN").as_bool())
+			f << (cell->getParam("\\SRC_POL").as_bool() ? "posedge ": "negedge ");
+		dump_sigspec(f, cell->getPort("\\SRC"));
+
+		if (cell->getPort("\\SRC_EN") != State::S1) {
+			f << " &&& ";
+			dump_sigspec(f, cell->getPort("\\SRC_EN"));
+		}
+
+		f << ", ";
+		if (cell->getParam("\\DST_PEN").as_bool())
+			f << (cell->getParam("\\DST_POL").as_bool() ? "posedge ": "negedge ");
+		dump_sigspec(f, cell->getPort("\\DST"));
+
+		if (cell->getPort("\\DST_EN") != State::S1) {
+			f << " &&& ";
+			dump_sigspec(f, cell->getPort("\\DST_EN"));
+		}
+
+		bool bak_decimal = decimal;
+		decimal = 1;
+
+		f << ", ";
+		dump_const(f, cell->getParam("\\T_LIMIT"));
+
+		if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") {
+			f << ", ";
+			dump_const(f, cell->getParam("\\T_LIMIT2"));
+		}
+
+		f << ");\n";
+		decimal = bak_decimal;
 
 		f << stringf("%s" "endspecify\n", indent.c_str());
 		return true;
@@ -1321,8 +1379,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			if (it != cell->parameters.begin())
 				f << stringf(",");
 			f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
-			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
-			dump_const(f, it->second, -1, 0, false, is_signed);
+			dump_const(f, it->second);
 			f << stringf(")");
 		}
 		f << stringf("\n%s" ")", indent.c_str());
@@ -1369,8 +1426,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	if (defparam && cell->parameters.size() > 0) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
-			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
-			dump_const(f, it->second, -1, 0, false, is_signed);
+			dump_const(f, it->second);
 			f << stringf(";\n");
 		}
 	}
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 92205b7ae..379fed641 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1492,10 +1492,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					continue;
 				}
 				if (child->type == AST_PARASET) {
+					int extra_const_flags = 0;
 					IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
 					if (child->children[0]->type == AST_REALVALUE) {
 						log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
 								log_id(cell), log_id(paraname), child->children[0]->realvalue);
+						extra_const_flags = RTLIL::CONST_FLAG_REAL;
 						auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
 						strnode->cloneInto(child->children[0]);
 						delete strnode;
@@ -1504,6 +1506,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
 								log_id(cell), log_id(paraname));
 					cell->parameters[paraname] = child->children[0]->asParaConst();
+					cell->parameters[paraname].flags |= extra_const_flags;
 					continue;
 				}
 				if (child->type == AST_ARGUMENT) {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index db5c33c73..0c3fa6f76 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -50,7 +50,7 @@ namespace RTLIL
 		CONST_FLAG_NONE   = 0,
 		CONST_FLAG_STRING = 1,
 		CONST_FLAG_SIGNED = 2,  // only used for parameters
-		CONST_FLAG_REAL   = 4   // unused -- to be used for parameters
+		CONST_FLAG_REAL   = 4   // only used for parameters
 	};
 
 	struct Const;

From 1cd1b5fc1adeb3ef62f061e27f5d8433d5c7dce6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 6 May 2019 12:00:40 +0200
Subject: [PATCH 21/22] Add "real" keyword to ilang format

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/ilang/ilang_backend.cc | 5 ++++-
 frontends/ilang/ilang_lexer.l   | 1 +
 frontends/ilang/ilang_parser.y  | 8 +++++++-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index dc39e5e08..04d1ee311 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -160,7 +160,10 @@ void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
 	}
 	f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
 	for (auto &it : cell->parameters) {
-		f << stringf("%s  parameter%s %s ", indent.c_str(), (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it.first.c_str());
+		f << stringf("%s  parameter%s%s %s ", indent.c_str(),
+				(it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
+				(it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
+				it.first.c_str());
 		dump_const(f, it.second);
 		f << stringf("\n");
 	}
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index d8e01ae4d..4fd0ae855 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -53,6 +53,7 @@ USING_YOSYS_NAMESPACE
 "attribute"	{ return TOK_ATTRIBUTE; }
 "parameter"	{ return TOK_PARAMETER; }
 "signed"	{ return TOK_SIGNED; }
+"real"		{ return TOK_REAL; }
 "wire"		{ return TOK_WIRE; }
 "memory"	{ return TOK_MEMORY; }
 "width"		{ return TOK_WIDTH; }
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index f83824088..e9961d02a 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -61,7 +61,7 @@ USING_YOSYS_NAMESPACE
 %token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC
 %token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_GLOBAL TOK_INIT
 %token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
-%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_UPTO
+%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_REAL TOK_UPTO
 
 %type <rsigspec> sigspec_list_reversed
 %type <sigspec> sigspec sigspec_list
@@ -241,6 +241,12 @@ cell_body:
 		free($4);
 		delete $5;
 	} |
+	cell_body TOK_PARAMETER TOK_REAL TOK_ID constant EOL {
+		current_cell->parameters[$4] = *$5;
+		current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_REAL;
+		free($4);
+		delete $5;
+	} |
 	cell_body TOK_CONNECT TOK_ID sigspec EOL {
 		if (current_cell->hasPort($3))
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());

From 8c6e94d57c430fc516dbcfbde312dbd7c860477b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 6 May 2019 12:26:15 +0200
Subject: [PATCH 22/22] Improve tests/various/specify.ys

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/various/specify.ys | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 87d98e0a0..a5ca07219 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -8,10 +8,12 @@ cd test2
 select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
+cd
 write_verilog specify.out
 design -stash gold
 
 read_verilog -specify specify.out
+prep
 cd test
 select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
@@ -20,7 +22,35 @@ cd test2
 select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
+cd
 design -stash gate
 
-# TODO: How to check $specify and $specrule-s are equivalent?
-#       Otherwise, need more select statements to check parameter values are as expected?
+design -copy-from gold -as gold test
+design -copy-from gate -as gate test
+rename -hide
+rename -enumerate -pattern A_% t:$specify3
+rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
+rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+select n:C_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset
+
+design -copy-from gold -as gold test2
+design -copy-from gate -as gate test2
+rename -hide
+rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
+rename -enumerate -pattern B_% t:$specify2 n:A_* %d
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset