mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-04 17:17:43 +00:00
Code Activity

quicklogic: fix double width read

Browse source
This commit is contained in:
Krystine Sherwin 2023-11-30 09:16:12 +13:00 • committed by Martin Povišer
parent 8d3b238b9b
commit 7513bfcbfe
2 changed files with 25 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
View file

@ -36,7 +36,7 @@ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
# 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K)
([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
# two disjoint 18K memories can share a single TDP36K
([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),