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Fix elaboration of whole memory words used as indices

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This commit is contained in:
Zachary Snow 2020-12-26 21:38:13 -07:00
parent af457ce8d0
commit 750831e3e0
4 changed files with 56 additions and 1 deletions
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23
tests/various/memory_word_as_index.ys Normal file
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read_verilog memory_word_as_index.v
hierarchy
proc
memory
flatten
opt -full
equiv_make gold gate1 equiv
equiv_simple
equiv_status -assert
delete equiv
equiv_make gold gate2 equiv
equiv_simple
equiv_status -assert
delete equiv
equiv_make gold gate3 equiv
equiv_simple
equiv_status -assert