Fix elaboration of whole memory words used as indices

tests/various/memory_word_as_index.data

@@ -0,0 +1,4 @@
+00 04 08 0c
+10 14 18 1c
+20 24 28 2c
+30 34 38 3c

tests/various/memory_word_as_index.v

@@ -0,0 +1,21 @@
+`define DATA 64'h492e5c4d7747e032
+
+`define GATE(n, expr) \
+module gate``n(sel, out); \
+	input wire [3:0] sel; \
+	output wire out; \
+	reg [63:0] bits; \
+	reg [5:0] ptrs[15:0]; \
+	initial bits = `DATA; \
+	initial $readmemh("memory_word_as_index.data", ptrs); \
+	assign out = expr; \
+endmodule
+
+`GATE(1, bits[ptrs[sel]])
+`GATE(2, bits[ptrs[sel][5:0]])
+`GATE(3, bits[ptrs[sel]+:1])
+
+module gold(sel, out);
+	input wire [3:0] sel;
+	output wire out = `DATA >> (sel * 4);
+endmodule

tests/various/memory_word_as_index.ys

@@ -0,0 +1,23 @@
+read_verilog memory_word_as_index.v
+
+hierarchy
+proc
+memory
+flatten
+opt -full
+
+equiv_make gold gate1 equiv
+equiv_simple
+equiv_status -assert
+
+delete equiv
+
+equiv_make gold gate2 equiv
+equiv_simple
+equiv_status -assert
+
+delete equiv
+
+equiv_make gold gate3 equiv
+equiv_simple
+equiv_status -assert