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Synthesis support for SystemVerilog interfaces

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This time doing the changes mostly in AST before RTLIL generation
This commit is contained in:
Ruben Undheim 2018-10-11 23:33:31 +02:00
parent 9850de405a
commit 75009ada3c
10 changed files with 501 additions and 21 deletions
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8
frontends/verilog/verilog_lexer.l
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@ -150,6 +150,9 @@ YOSYS_NAMESPACE_END
"specparam" { return TOK_SPECPARAM; }
"package" { SV_KEYWORD(TOK_PACKAGE); }
"endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
"interface" { SV_KEYWORD(TOK_INTERFACE); }
"endinterface" { SV_KEYWORD(TOK_ENDINTERFACE); }
"modport" { SV_KEYWORD(TOK_MODPORT); }
"parameter" { return TOK_PARAMETER; }
"localparam" { return TOK_LOCALPARAM; }
"defparam" { return TOK_DEFPARAM; }
@ -295,6 +298,11 @@ supply1 { return TOK_SUPPLY1; }
return TOK_ID;
}
[a-zA-Z_$][a-zA-Z0-9_$\.]* {
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_ID;
}
"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
static bool printed_warning = false;
if (!printed_warning) {