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Add support for DREG

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This commit is contained in:
Eddie Hung 2019-09-06 15:32:26 -07:00
parent ef56f8596f
commit 74eac76699
2 changed files with 70 additions and 2 deletions
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13
passes/pmgen/xilinx_dsp.cc
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@ -38,6 +38,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
log("ffB: %s\n", log_id(st.ffB, "--"));
log("ffBmux: %s\n", log_id(st.ffBmux, "--"));
log("ffD: %s\n", log_id(st.ffD, "--"));
log("ffDmux: %s\n", log_id(st.ffDmux, "--"));
log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("ffMmux: %s\n", log_id(st.ffMmux, "--"));
@ -141,6 +143,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
cell->setParam("\\BREG", 1);
}
if (st.ffD) {
if (st.ffDmux) {
SigSpec S = st.ffDmux->getPort("\\S");
cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
}
else
cell->setPort("\\CED", State::S1);
cell->setPort("\\D", st.sigD);
cell->setParam("\\DREG", 1);
}
if (st.ffM) {
if (st.ffMmux) {
SigSpec S = st.ffMmux->getPort("\\S");