diff --git a/tests/verific/mixed_flist.flist b/tests/verific/mixed_flist.flist
new file mode 100644
index 000000000..d4edb8532
--- /dev/null
+++ b/tests/verific/mixed_flist.flist
@@ -0,0 +1,2 @@
+mixed_flist.sv
+mixed_flist.vhd
diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv
new file mode 100644
index 000000000..83c04054f
--- /dev/null
+++ b/tests/verific/mixed_flist.sv
@@ -0,0 +1,3 @@
+module sv_top(input logic a, output logic y);
+	assign y = a;
+endmodule
diff --git a/tests/verific/mixed_flist.vhd b/tests/verific/mixed_flist.vhd
new file mode 100644
index 000000000..25a10f963
--- /dev/null
+++ b/tests/verific/mixed_flist.vhd
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_mod is
+	port (
+		a : in std_logic;
+		y : out std_logic
+	);
+end entity vhdl_mod;
+
+architecture rtl of vhdl_mod is
+begin
+	y <= a;
+end architecture rtl;
diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys
new file mode 100644
index 000000000..4cbdb1e59
--- /dev/null
+++ b/tests/verific/mixed_flist.ys
@@ -0,0 +1,5 @@
+verific -f -sv mixed_flist.flist
+verific -import sv_top
+verific -import vhdl_mod
+select -assert-mod-count 1 sv_top
+select -assert-mod-count 1 vhdl_mod