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Remove output_bits

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This commit is contained in:
Eddie Hung 2019-08-22 11:14:59 -07:00
parent 231ddbf95c
commit 74bd190d3b
2 changed files with 7 additions and 16 deletions
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13
passes/pmgen/xilinx_srl.cc
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@ -214,19 +214,8 @@ struct XilinxSrlPass : public Pass {
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
pm.run_fixed(run_fixed); pm.run_fixed(run_fixed);
} }
if (variable) { if (variable)
// Since `nusers` does not count module ports as a user,
// and since `sigmap` does not always make such ports
// the canonical signal.. need to maintain a pool these
// ourselves
for (auto p : module->ports) {
auto w = module->wire(p);
if (w->port_output)
for (auto b : pm.sigmap(w))
pm.ud_variable.output_bits.insert(b);
}
pm.run_variable(run_variable); pm.run_variable(run_variable);
}
} }
} }
} XilinxSrlPass; } XilinxSrlPass;

10
passes/pmgen/xilinx_srl.pmg
View file

@ -152,13 +152,12 @@ pattern variable
state <int> shiftx_width state <int> shiftx_width
udata <int> minlen udata <int> minlen
udata <pool<SigBit>> output_bits
udata <vector<Cell*>> chain udata <vector<Cell*>> chain
match shiftx match shiftx
select shiftx->type.in($shiftx) select shiftx->type.in($shiftx)
select !shiftx->has_keep_attr() select !shiftx->has_keep_attr()
select param(shiftx, \Y_WIDTH) == 1 select param(shiftx, \Y_WIDTH).as_int() == 1
filter param(shiftx, \A_WIDTH).as_int() >= minlen filter param(shiftx, \A_WIDTH).as_int() >= minlen
endmatch endmatch
@ -170,7 +169,6 @@ match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)
select nusers(port(first, \Q)) == 2 select nusers(port(first, \Q)) == 2
index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1] index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1]
filter !output_bits.count(port(first, \Q))
endmatch endmatch
code code
@ -194,7 +192,6 @@ match next
select !next->has_keep_attr() select !next->has_keep_attr()
select !port(next, \D)[0].wire->get_bool_attribute(\keep) select !port(next, \D)[0].wire->get_bool_attribute(\keep)
select nusers(port(next, \Q)) == 3 select nusers(port(next, \Q)) == 3
filter !output_bits.count(port(next, \Q))
index <IdString> next->type === chain.back()->type index <IdString> next->type === chain.back()->type
index <SigBit> port(next, \Q) === port(chain.back(), \D) index <SigBit> port(next, \Q) === port(chain.back(), \D)
index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
@ -202,6 +199,11 @@ endmatch
code code
if (next) { if (next) {
auto sig = port(next, \Q);
log_warning("nusers of '%s'\n", log_signal(sig));
for (auto bit : sigmap(sig))
for (auto user : sigusers[bit])
log_warning("\t%s\n", log_id(user));
chain.push_back(next); chain.push_back(next);
if (GetSize(chain) < shiftx_width) if (GetSize(chain) < shiftx_width)
subpattern(tail); subpattern(tail);