From 748600c1679674633c98117e8dac06b9fbcbde3e Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Wed, 14 May 2025 14:18:57 +0100
Subject: [PATCH] small whitespace cleanup (#5119)

---
 kernel/rtlil.h         |  2 +-
 passes/opt/opt_expr.cc | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 96c8c523b..3ef092c08 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1182,7 +1182,7 @@ struct RTLIL::Selection
 		bool boxes = false,
 		// the design to select from
 		RTLIL::Design *design = nullptr
-	) : 
+	) :
 		selects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }
 
 	// checks if the given module exists in the current design and is a
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 74f5b386a..742fb0029 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -487,7 +487,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
 		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
-		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);	
+		handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
 	}
 
 	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
@@ -1715,22 +1715,22 @@ skip_identity:
 
 			if (onehot) {
 				if (bit_idx == 1) {
-					log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n", 
+					log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n",
 							cell->name.c_str(), module->name.c_str());
 					cell->type = ID($shl);
 					cell->parameters[ID::A_WIDTH] = 1;
 					cell->setPort(ID::A, Const(State::S1, 1));
 				}
 				else {
-					log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n", 
+					log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n",
 							cell->name.c_str(), module->name.c_str());
 					cell->type = ID($mul);
 					cell->parameters[ID::A_SIGNED] = 0;
 					cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
-					
+
 					SigSpec y_wire = module->addWire(NEW_ID, y_size);
 					cell->setPort(ID::Y, y_wire);
-					
+
 					module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
 				}
 				did_something = true;