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Add latch inference msg severity option.

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nella 2026-06-15 14:17:02 +02:00
parent 8869ce61dc
commit 7473fcf939
4 changed files with 97 additions and 7 deletions
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32
tests/proc/proc_latches.ys Normal file
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# warn
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect warning "Latch inferred for signal" 1
proc
logger -check-expected
design -reset
# auto
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
proc -latches auto
logger -check-expected
design -reset
# error
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect error "Latch inferred for signal" 1
proc -latches error