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https://github.com/YosysHQ/yosys
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Make SigSpec::unpack() non-const
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parent
870ae18a2d
commit
745222fa3b
2 changed files with 71 additions and 66 deletions
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@ -1223,9 +1223,10 @@ struct RTLIL::SigSpecConstIterator
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typedef RTLIL::SigBit& reference;
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const RTLIL::SigSpec *sig_p;
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RTLIL::SigBit bit;
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int index;
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inline const RTLIL::SigBit &operator*() const;
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inline const RTLIL::SigBit &operator*();
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inline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }
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inline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }
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inline void operator++() { index++; }
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@ -1251,8 +1252,8 @@ private:
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new (&bits_) std::vector<RTLIL::SigBit>;
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}
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void unpack() const;
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inline void inline_unpack() const {
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void unpack();
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inline void inline_unpack() {
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if (rep_ == CHUNK)
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unpack();
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}
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@ -1406,13 +1407,22 @@ public:
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friend struct Chunks::const_iterator;
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inline Chunks chunks() const { return {*this}; }
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inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
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inline const SigSpec &bits() const { return *this; }
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inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); }
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inline bool empty() const { return size() == 0; }
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inline RTLIL::SigBit &operator[](int index) { inline_unpack(); hash_ = 0; return bits_.at(index); }
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inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }
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inline RTLIL::SigBit operator[](int index) const {
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if (rep_ == CHUNK) {
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if (index < 0 || index >= chunk_.width)
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throw std::out_of_range("SigSpec::operator[]");
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if (chunk_.wire)
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return RTLIL::SigBit(chunk_.wire, chunk_.offset + index);
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return RTLIL::SigBit(chunk_.data[index]);
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}
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return bits_.at(index);
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}
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inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
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inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = size(); return it; }
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@ -1456,6 +1466,8 @@ public:
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RTLIL::SigBit lsb() const { log_assert(size()); return (*this)[0]; };
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RTLIL::SigBit msb() const { log_assert(size()); return (*this)[size() - 1]; };
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RTLIL::SigBit front() const { return (*this)[0]; }
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RTLIL::SigBit back() const { return (*this)[size() - 1]; }
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void append(const RTLIL::SigSpec &signal);
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inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }
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@ -1536,7 +1548,7 @@ public:
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static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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operator std::vector<RTLIL::SigChunk>() const;
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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operator std::vector<RTLIL::SigBit>() const { return to_sigbit_vector(); }
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const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < size() ? (*this)[offset] : defval; }
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[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }
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@ -2444,8 +2456,9 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
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return (*sig_p)[index];
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}
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inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
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return (*sig_p)[index];
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inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() {
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bit = (*sig_p)[index];
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return bit;
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}
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inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
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