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Add INIT parameter to all ff/latch cells

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This commit is contained in:
Eddie Hung 2019-02-06 14:16:26 -08:00
parent 115883f467
commit 742b4e01b4
2 changed files with 86 additions and 43 deletions
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111
techlibs/common/simcells.v
View file

@ -451,8 +451,9 @@ endmodule
//- 1 1 | y //- 1 1 | y
//- //-
module \$_SR_NN_ (S, R, Q); module \$_SR_NN_ (S, R, Q);
parameter INIT = 1'bx;
input S, R; input S, R;
output reg Q; output reg Q = INIT;
always @(negedge S, negedge R) begin always @(negedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -475,8 +476,9 @@ endmodule
//- 1 0 | y //- 1 0 | y
//- //-
module \$_SR_NP_ (S, R, Q); module \$_SR_NP_ (S, R, Q);
parameter INIT = 1'bx;
input S, R; input S, R;
output reg Q; output reg Q = INIT;
always @(negedge S, posedge R) begin always @(negedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -499,8 +501,9 @@ endmodule
//- 0 1 | y //- 0 1 | y
//- //-
module \$_SR_PN_ (S, R, Q); module \$_SR_PN_ (S, R, Q);
parameter INIT = 1'bx;
input S, R; input S, R;
output reg Q; output reg Q = INIT;
always @(posedge S, negedge R) begin always @(posedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -523,8 +526,9 @@ endmodule
//- 0 0 | y //- 0 0 | y
//- //-
module \$_SR_PP_ (S, R, Q); module \$_SR_PP_ (S, R, Q);
parameter INIT = 1'bx;
input S, R; input S, R;
output reg Q; output reg Q = INIT;
always @(posedge S, posedge R) begin always @(posedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -542,8 +546,9 @@ endmodule
//- type is usually only used in netlists for formal verification.) //- type is usually only used in netlists for formal verification.)
//- //-
module \$_FF_ (D, Q); module \$_FF_ (D, Q);
parameter INIT = 1'bx;
input D; input D;
output reg Q; output reg Q = INIT;
always @($global_clock) begin always @($global_clock) begin
Q <= D; Q <= D;
end end
@ -562,8 +567,9 @@ endmodule
//- - - | q //- - - | q
//- //-
module \$_DFF_N_ (D, C, Q); module \$_DFF_N_ (D, C, Q);
parameter INIT = 1'bx;
input D, C; input D, C;
output reg Q; output reg Q = INIT;
always @(negedge C) begin always @(negedge C) begin
Q <= D; Q <= D;
end end
@ -581,8 +587,9 @@ endmodule
//- - - | q //- - - | q
//- //-
module \$_DFF_P_ (D, C, Q); module \$_DFF_P_ (D, C, Q);
parameter INIT = 1'bx;
input D, C; input D, C;
output reg Q; output reg Q = INIT;
always @(posedge C) begin always @(posedge C) begin
Q <= D; Q <= D;
end end
@ -600,8 +607,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFFE_NN_ (D, C, E, Q); module \$_DFFE_NN_ (D, C, E, Q);
parameter INIT = 1'bx;
input D, C, E; input D, C, E;
output reg Q; output reg Q = INIT;
always @(negedge C) begin always @(negedge C) begin
if (!E) Q <= D; if (!E) Q <= D;
end end
@ -619,8 +627,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFFE_NP_ (D, C, E, Q); module \$_DFFE_NP_ (D, C, E, Q);
parameter INIT = 1'bx;
input D, C, E; input D, C, E;
output reg Q; output reg Q = INIT;
always @(negedge C) begin always @(negedge C) begin
if (E) Q <= D; if (E) Q <= D;
end end
@ -638,8 +647,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFFE_PN_ (D, C, E, Q); module \$_DFFE_PN_ (D, C, E, Q);
parameter INIT = 1'bx;
input D, C, E; input D, C, E;
output reg Q; output reg Q = INIT;
always @(posedge C) begin always @(posedge C) begin
if (!E) Q <= D; if (!E) Q <= D;
end end
@ -657,8 +667,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFFE_PP_ (D, C, E, Q); module \$_DFFE_PP_ (D, C, E, Q);
parameter INIT = 1'bx;
input D, C, E; input D, C, E;
output reg Q; output reg Q = INIT;
always @(posedge C) begin always @(posedge C) begin
if (E) Q <= D; if (E) Q <= D;
end end
@ -677,8 +688,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_NN0_ (D, C, R, Q); module \$_DFF_NN0_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(negedge C or negedge R) begin always @(negedge C or negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -700,8 +712,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_NN1_ (D, C, R, Q); module \$_DFF_NN1_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(negedge C or negedge R) begin always @(negedge C or negedge R) begin
if (R == 0) if (R == 0)
Q <= 1; Q <= 1;
@ -723,8 +736,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_NP0_ (D, C, R, Q); module \$_DFF_NP0_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(negedge C or posedge R) begin always @(negedge C or posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -746,8 +760,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_NP1_ (D, C, R, Q); module \$_DFF_NP1_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(negedge C or posedge R) begin always @(negedge C or posedge R) begin
if (R == 1) if (R == 1)
Q <= 1; Q <= 1;
@ -769,8 +784,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_PN0_ (D, C, R, Q); module \$_DFF_PN0_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(posedge C or negedge R) begin always @(posedge C or negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -792,8 +808,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_PN1_ (D, C, R, Q); module \$_DFF_PN1_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(posedge C or negedge R) begin always @(posedge C or negedge R) begin
if (R == 0) if (R == 0)
Q <= 1; Q <= 1;
@ -815,8 +832,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_PP0_ (D, C, R, Q); module \$_DFF_PP0_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(posedge C or posedge R) begin always @(posedge C or posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -838,8 +856,9 @@ endmodule
//- - - - | q //- - - - | q
//- //-
module \$_DFF_PP1_ (D, C, R, Q); module \$_DFF_PP1_ (D, C, R, Q);
parameter INIT = 1'bx;
input D, C, R; input D, C, R;
output reg Q; output reg Q = INIT;
always @(posedge C or posedge R) begin always @(posedge C or posedge R) begin
if (R == 1) if (R == 1)
Q <= 1; Q <= 1;
@ -862,8 +881,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_NNN_ (C, S, R, D, Q); module \$_DFFSR_NNN_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(negedge C, negedge S, negedge R) begin always @(negedge C, negedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -889,8 +909,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_NNP_ (C, S, R, D, Q); module \$_DFFSR_NNP_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(negedge C, negedge S, posedge R) begin always @(negedge C, negedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -916,8 +937,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_NPN_ (C, S, R, D, Q); module \$_DFFSR_NPN_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(negedge C, posedge S, negedge R) begin always @(negedge C, posedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -942,8 +964,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_NPP_ (C, S, R, D, Q); module \$_DFFSR_NPP_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(negedge C, posedge S, posedge R) begin always @(negedge C, posedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -968,8 +991,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_PNN_ (C, S, R, D, Q); module \$_DFFSR_PNN_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(posedge C, negedge S, negedge R) begin always @(posedge C, negedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -995,8 +1019,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_PNP_ (C, S, R, D, Q); module \$_DFFSR_PNP_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(posedge C, negedge S, posedge R) begin always @(posedge C, negedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -1022,8 +1047,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_PPN_ (C, S, R, D, Q); module \$_DFFSR_PPN_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(posedge C, posedge S, negedge R) begin always @(posedge C, posedge S, negedge R) begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -1048,8 +1074,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DFFSR_PPP_ (C, S, R, D, Q); module \$_DFFSR_PPP_ (C, S, R, D, Q);
parameter INIT = 1'bx;
input C, S, R, D; input C, S, R, D;
output reg Q; output reg Q = INIT;
always @(posedge C, posedge S, posedge R) begin always @(posedge C, posedge S, posedge R) begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -1072,8 +1099,9 @@ endmodule
//- - - | q //- - - | q
//- //-
module \$_DLATCH_N_ (E, D, Q); module \$_DLATCH_N_ (E, D, Q);
parameter INIT = 1'bx;
input E, D; input E, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (E == 0) if (E == 0)
Q <= D; Q <= D;
@ -1092,8 +1120,9 @@ endmodule
//- - - | q //- - - | q
//- //-
module \$_DLATCH_P_ (E, D, Q); module \$_DLATCH_P_ (E, D, Q);
parameter INIT = 1'bx;
input E, D; input E, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (E == 1) if (E == 1)
Q <= D; Q <= D;
@ -1114,8 +1143,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_NNN_ (E, S, R, D, Q); module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -1141,8 +1171,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_NNP_ (E, S, R, D, Q); module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -1168,8 +1199,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_NPN_ (E, S, R, D, Q); module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -1194,8 +1226,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_NPP_ (E, S, R, D, Q); module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -1220,8 +1253,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_PNN_ (E, S, R, D, Q); module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -1247,8 +1281,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_PNP_ (E, S, R, D, Q); module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;
@ -1274,8 +1309,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_PPN_ (E, S, R, D, Q); module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 0) if (R == 0)
Q <= 0; Q <= 0;
@ -1300,8 +1336,9 @@ endmodule
//- - - - - | q //- - - - - | q
//- //-
module \$_DLATCHSR_PPP_ (E, S, R, D, Q); module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
parameter INIT = 1'bx;
input E, S, R, D; input E, S, R, D;
output reg Q; output reg Q = INIT;
always @* begin always @* begin
if (R == 1) if (R == 1)
Q <= 0; Q <= 0;

18
techlibs/common/simlib.v
View file

@ -1464,10 +1464,11 @@ module \$dff (CLK, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}};
input CLK; input CLK;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY; wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin always @(posedge pos_clk) begin
@ -1483,10 +1484,11 @@ module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}};
input CLK, EN; input CLK, EN;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY; wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin always @(posedge pos_clk) begin
@ -1504,10 +1506,11 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}};
input CLK; input CLK;
input [WIDTH-1:0] SET, CLR, D; input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY; wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET; wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@ -1537,10 +1540,11 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1; parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0; parameter ARST_VALUE = 0;
parameter INIT = {WIDTH{1'bx}};
input CLK, ARST; input CLK, ARST;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY; wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY; wire pos_arst = ARST == ARST_POLARITY;
@ -1559,10 +1563,11 @@ module \$dlatch (EN, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}};
input EN; input EN;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
always @* begin always @* begin
if (EN == EN_POLARITY) if (EN == EN_POLARITY)
@ -1580,10 +1585,11 @@ parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}};
input EN; input EN;
input [WIDTH-1:0] SET, CLR, D; input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q; output reg [WIDTH-1:0] Q = INIT;
wire pos_en = EN == EN_POLARITY; wire pos_en = EN == EN_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET; wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;