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quicklogic: Move pp3 tests one level down

This commit is contained in:
Martin Povišer 2023-10-09 13:13:42 +02:00
parent f84ab98055
commit 74296e3d92
11 changed files with 11 additions and 11 deletions

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@ -1,13 +0,0 @@
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 2 t:inpad
select -assert-count 1 t:outpad
select -assert-count 1 t:$_TBUF_
select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D