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quicklogic: Move pp3 tests one level down
This commit is contained in:
Martin Povišer
parent
f84ab98055
commit
74296e3d92
11 changed files with 11 additions and 11 deletions
11
tests/arch/quicklogic/pp3/add_sub.ys
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11
tests/arch/quicklogic/pp3/add_sub.ys
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read_verilog ../../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT2
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select -assert-count 8 t:LUT3
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select -assert-count 2 t:LUT4
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select -assert-count 8 t:inpad
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select -assert-count 8 t:outpad
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select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
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67
tests/arch/quicklogic/pp3/adffs.ys
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67
tests/arch/quicklogic/pp3/adffs.ys
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read_verilog ../../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 1 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 2 t:ckpad
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select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 2 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 4 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT1 t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad %% t:* %D
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18
tests/arch/quicklogic/pp3/counter.ys
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18
tests/arch/quicklogic/pp3/counter.ys
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read_verilog ../../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -multiclock -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 3 t:LUT2
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select -assert-count 5 t:LUT3
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select -assert-count 1 t:LUT4
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select -assert-count 8 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 8 t:outpad
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select -assert-count 2 t:ckpad
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select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D
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33
tests/arch/quicklogic/pp3/dffs.ys
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33
tests/arch/quicklogic/pp3/dffs.ys
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read_verilog ../../common/dffs.v
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rename dff my_dff # Work around conflicting module names between test and vendor cells
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rename dffe my_dffe
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design -save read
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hierarchy -top my_dff
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd my_dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:ckpad
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:inpad
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 1 t:outpad
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select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D
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design -load read
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hierarchy -top my_dffe
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd my_dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:ckpad
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select -assert-count 1 t:dffepc
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select -assert-count 2 t:inpad
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:outpad
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select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D
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23
tests/arch/quicklogic/pp3/fsm.ys
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23
tests/arch/quicklogic/pp3/fsm.ys
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read_verilog ../../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 9 t:LUT3
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select -assert-count 4 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 3 t:inpad
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select -assert-count 2 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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40
tests/arch/quicklogic/pp3/latches.ys
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40
tests/arch/quicklogic/pp3/latches.ys
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read_verilog ../../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:LUT4
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select -assert-count 5 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
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14
tests/arch/quicklogic/pp3/logic.ys
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14
tests/arch/quicklogic/pp3/logic.ys
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@ -0,0 +1,14 @@
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read_verilog ../../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 6 t:LUT2
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select -assert-count 2 t:LUT3
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select -assert-count 8 t:inpad
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select -assert-count 10 t:outpad
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select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D
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52
tests/arch/quicklogic/pp3/mux.ys
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52
tests/arch/quicklogic/pp3/mux.ys
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read_verilog ../../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 3 t:LUT3
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select -assert-count 6 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:LUT3
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select -assert-count 2 t:mux4x0
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select -assert-count 11 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 2 t:mux8x0
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select -assert-count 20 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:mux8x0 t:inpad t:outpad %% t:* %D
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4
tests/arch/quicklogic/pp3/run-test.sh
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4
tests/arch/quicklogic/pp3/run-test.sh
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#!/usr/bin/env bash
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set -eu
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source ../../../gen-tests-makefile.sh
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run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
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13
tests/arch/quicklogic/pp3/tribuf.ys
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13
tests/arch/quicklogic/pp3/tribuf.ys
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read_verilog ../../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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select -assert-count 2 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 1 t:$_TBUF_
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select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D
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