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quicklogic: Move pp3 tests one level down

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This commit is contained in:
Martin Povišer 2023-10-09 13:13:42 +02:00
parent f84ab98055
commit 74296e3d92
11 changed files with 11 additions and 11 deletions
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14
tests/arch/quicklogic/logic.ys
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@ -1,14 +0,0 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT3
select -assert-count 8 t:inpad
select -assert-count 10 t:outpad
select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D