mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-11 02:08:08 +00:00
s/NEW_ID/NEWER_ID/g
This commit is contained in:
parent
6b9082fa64
commit
73d51b25d6
130 changed files with 1275 additions and 1275 deletions
|
@ -89,7 +89,7 @@ finally
|
|||
|
||||
if (i % MAX_DSP_CASCADE > 0) {
|
||||
if (P >= 0) {
|
||||
Wire *cascade = module->addWire(NEW_ID, 48);
|
||||
Wire *cascade = module->addWire(NEWER_ID, 48);
|
||||
dsp_pcin->setPort(ID(C), Const(0, 48));
|
||||
dsp_pcin->setPort(ID(PCIN), cascade);
|
||||
dsp->setPort(ID(PCOUT), cascade);
|
||||
|
@ -117,7 +117,7 @@ finally
|
|||
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
|
||||
}
|
||||
if (AREG >= 0) {
|
||||
Wire *cascade = module->addWire(NEW_ID, 30);
|
||||
Wire *cascade = module->addWire(NEWER_ID, 30);
|
||||
dsp_pcin->setPort(ID(A), Const(0, 30));
|
||||
dsp_pcin->setPort(ID(ACIN), cascade);
|
||||
dsp->setPort(ID(ACOUT), cascade);
|
||||
|
@ -131,7 +131,7 @@ finally
|
|||
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
|
||||
}
|
||||
if (BREG >= 0) {
|
||||
Wire *cascade = module->addWire(NEW_ID, 18);
|
||||
Wire *cascade = module->addWire(NEWER_ID, 18);
|
||||
if (dsp->type.in(\DSP48A, \DSP48A1)) {
|
||||
// According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
|
||||
// "The DSP48A1 component uses this input when cascading
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue