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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -127,7 +127,7 @@ struct QlBramMergeWorker {
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
RTLIL::Cell* merged = module->addCell(NEWER_ID, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
for (auto &it : param_map(false))

10
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -80,7 +80,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
log(" %s (%s)\n", log_id(cell), log_id(cell->type));
// Add the DSP cell
RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
RTLIL::Cell *cell = pm.module->addCell(NEWER_ID, type);
// Set attributes
cell->set_bool_attribute(ID(is_inferred), true);
@ -102,7 +102,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Connect output data port, pad if needed
if ((size_t) GetSize(sig_z) < tgt_z_width) {
auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
auto *wire = pm.module->addWire(NEWER_ID, tgt_z_width - GetSize(sig_z));
sig_z.append(wire);
}
cell->setPort(ID(z_o), sig_z);
@ -115,7 +115,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
if (st.ff->hasPort(ID(ARST))) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
rst = pm.module->Not(NEWER_ID, st.ff->getPort(ID(ARST)));
} else {
rst = st.ff->getPort(ID(ARST));
}
@ -125,7 +125,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
if (st.ff->hasPort(ID(EN))) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
ena = pm.module->Not(NEWER_ID, st.ff->getPort(ID(EN)));
} else {
ena = st.ff->getPort(ID(EN));
}
@ -143,7 +143,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Depending on the mux port ordering insert inverter if needed
log_assert(st.mux_ab.in(ID(A), ID(B)));
if (st.mux_ab == ID(A))
sig_s = pm.module->Not(NEW_ID, sig_s);
sig_s = pm.module->Not(NEWER_ID, sig_s);
// Assemble the full control signal for the feedback_i port
RTLIL::SigSpec sig_f;

4
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -148,7 +148,7 @@ struct QlDspSimdPass : public Pass {
Cell *dsp_b = group[i + 1];
// Create the new cell
Cell *simd = module->addCell(NEW_ID, m_SimdDspType);
Cell *simd = module->addCell(NEWER_ID, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type),
log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type));
@ -182,7 +182,7 @@ struct QlDspSimdPass : public Pass {
if (!isOutput)
sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding));
else
sigspec.append(module->addWire(NEW_ID, padding));
sigspec.append(module->addWire(NEWER_ID, padding));
}
return sigspec;
};

4
techlibs/quicklogic/ql_ioff.cc
View file

@ -91,7 +91,7 @@ struct QlIoffPass : public Pass {
if (std::any_of(ioff_cells.begin(), ioff_cells.end(), [](Cell * c) { return c != nullptr; }))
{
// create replacement output wire
RTLIL::Wire* new_port_output = module->addWire(NEW_ID, old_port_output->width);
RTLIL::Wire* new_port_output = module->addWire(NEWER_ID, old_port_output->width);
new_port_output->start_offset = old_port_output->start_offset;
module->swap_names(old_port_output, new_port_output);
std::swap(old_port_output->port_id, new_port_output->port_id);
@ -108,7 +108,7 @@ struct QlIoffPass : public Pass {
if (ioff_cells[i]) {
log("Promoting %s to output IOFF.\n", log_signal(sig_n[i]));
RTLIL::Cell *new_cell = module->addCell(NEW_ID, ID(dff));
RTLIL::Cell *new_cell = module->addCell(NEWER_ID, ID(dff));
new_cell->setPort(ID::C, ioff_cells[i]->getPort(ID::C));
new_cell->setPort(ID::D, ioff_cells[i]->getPort(ID::D));
new_cell->setPort(ID::Q, sig_n[i]);