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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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6
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -79,9 +79,9 @@ static void fix_carry_chain(Module *module)
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);
Cell *c = module->addCell(NEWER_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEWER_ID);
SigBit dummy_bit = module->addWire(NEWER_ID);
SigSpec bits;
bits.append(dummy_bit);
bits.append(new_bit);

4
techlibs/efinix/efinix_fixcarry.cc
View file

@ -75,8 +75,8 @@ static void fix_carry_chain(Module *module)
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
Cell *c = module->addCell(NEW_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_ID);
Cell *c = module->addCell(NEWER_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEWER_ID);
c->setParam(ID(I0_POLARITY), State::S1);
c->setParam(ID(I1_POLARITY), State::S1);
c->setPort(ID(I0), bit);

2
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -162,7 +162,7 @@ struct FoldInvWorker {
continue;
// Create a duplicate of the LUT with an inverted output
// (if the uninverted version becomes unused it will be swept away)
Cell *dup_lut = module->addCell(NEW_ID, orig_lut->type);
Cell *dup_lut = module->addCell(NEWER_ID, orig_lut->type);
inv->unsetPort(ID::Y);
dup_lut->setPort(ID::O, inv_y);
for (auto conn : orig_lut->connections()) {

30
techlibs/ice40/ice40_dsp.cc
View file

@ -66,7 +66,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
cell = pm.module->addCell(NEWER_ID, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
}
else log_assert(cell->type == ID(SB_MAC16));
@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec AHOLD, BHOLD, CDHOLD;
if (st.ffA && st.ffA->hasPort(ID::EN))
AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(ID::EN)) : st.ffA->getPort(ID::EN);
AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffA->getPort(ID::EN)) : st.ffA->getPort(ID::EN);
else
AHOLD = State::S0;
if (st.ffB && st.ffB->hasPort(ID::EN))
BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(ID::EN)) : st.ffB->getPort(ID::EN);
BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffB->getPort(ID::EN)) : st.ffB->getPort(ID::EN);
else
BHOLD = State::S0;
if (st.ffCD && st.ffCD->hasPort(ID::EN))
CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(ID::EN)) : st.ffCD->getPort(ID::EN);
CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffCD->getPort(ID::EN)) : st.ffCD->getPort(ID::EN);
else
CDHOLD = State::S0;
cell->setPort(ID(AHOLD), AHOLD);
@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec IRSTTOP, IRSTBOT;
if (st.ffA && st.ffA->hasPort(ID::ARST))
IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(ID::ARST));
IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffA->getPort(ID::ARST));
else
IRSTTOP = State::S0;
if (st.ffB && st.ffB->hasPort(ID::ARST))
IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(ID::ARST));
IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffB->getPort(ID::ARST));
else
IRSTBOT = State::S0;
cell->setPort(ID(IRSTTOP), IRSTTOP);
@ -164,12 +164,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Cascade Interface
cell->setPort(ID(SIGNEXTIN), State::Sx);
cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEWER_ID));
cell->setPort(ID::CI, State::Sx);
cell->setPort(ID(ACCUMCI), State::Sx);
cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
cell->setPort(ID(ACCUMCO), pm.module->addWire(NEWER_ID));
// SB_MAC16 Output Interface
@ -185,10 +185,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
O.remove(O_width-1);
}
else
cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
cell->setPort(ID::CO, pm.module->addWire(NEWER_ID));
log_assert(GetSize(O) <= 32);
if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
O.append(pm.module->addWire(NEWER_ID, 32-GetSize(O)));
cell->setPort(ID::O, O);
@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec OHOLD;
if (st.ffO && st.ffO->hasPort(ID::EN))
OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(ID::EN)) : st.ffO->getPort(ID::EN);
OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEWER_ID, st.ffO->getPort(ID::EN)) : st.ffO->getPort(ID::EN);
else
OHOLD = State::S0;
cell->setPort(ID(OHOLDTOP), OHOLD);
@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec ORST;
if (st.ffO && st.ffO->hasPort(ID::ARST))
ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(ID::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::ARST));
ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(ID::ARST) : pm.module->Not(NEWER_ID, st.ffO->getPort(ID::ARST));
else
ORST = State::S0;
cell->setPort(ID(ORSTTOP), ORST);
@ -227,9 +227,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.muxAB == ID::A)
acc_reset = st.mux->getPort(ID::S);
else
acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
acc_reset = pm.module->Not(NEWER_ID, st.mux->getPort(ID::S));
} else if (st.ffO && st.ffO->hasPort(ID::SRST)) {
acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(ID::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(ID::SRST));
acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(ID::SRST) : pm.module->Not(NEWER_ID, st.ffO->getPort(ID::SRST));
}
cell->setPort(ID(OLOADTOP), acc_reset);
cell->setPort(ID(OLOADBOT), acc_reset);
@ -259,7 +259,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
else
cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEWER_ID, GetSize(O)));
cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
}
else {

2
techlibs/ice40/ice40_dsp.pmg
View file

@ -66,7 +66,7 @@ code sigA sigB sigH
wire_width++;
else {
if (wire_width) { // add empty wires for bit offset if needed
sigH.append(module->addWire(NEW_ID, wire_width));
sigH.append(module->addWire(NEWER_ID, wire_width));
wire_width = 0;
}
sigH.append(O[j]);

6
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -37,7 +37,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER));
Cell *cell = pm.module->addCell(NEWER_ID, ID($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry);
cell->setPort(ID::A, st.carry->getPort(ID(I0)));
@ -116,13 +116,13 @@ struct Ice40WrapCarryPass : public Pass {
if (cell->type != ID($__ICE40_CARRY_WRAPPER))
continue;
auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
auto carry = module->addCell(NEWER_ID, ID(SB_CARRY));
carry->setPort(ID(I0), cell->getPort(ID::A));
carry->setPort(ID(I1), cell->getPort(ID::B));
carry->setPort(ID::CI, cell->getPort(ID::CI));
carry->setPort(ID::CO, cell->getPort(ID::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEWER_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut));
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));

10
techlibs/microchip/microchip_dffopt.cc
View file

@ -309,22 +309,22 @@ struct MicrochipDffOptPass : public Pass {
Cell *lut_cell = nullptr;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_ID, ID(CFG1));
lut_cell = module->addCell(NEWER_ID, ID(CFG1));
break;
case 2:
lut_cell = module->addCell(NEW_ID, ID(CFG2));
lut_cell = module->addCell(NEWER_ID, ID(CFG2));
break;
case 3:
lut_cell = module->addCell(NEW_ID, ID(CFG3));
lut_cell = module->addCell(NEWER_ID, ID(CFG3));
break;
case 4:
lut_cell = module->addCell(NEW_ID, ID(CFG4));
lut_cell = module->addCell(NEWER_ID, ID(CFG4));
break;
default:
log_assert(!"unknown lut size");
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
Wire *lut_out = module->addWire(NEWER_ID);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::Y, lut_out);

16
techlibs/microchip/microchip_dsp.cc
View file

@ -98,12 +98,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEWER_ID, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(ID::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEWER_ID, arst));
} else {
// active low async/sync rst
cell->setPort(rstport, State::S1);
@ -113,7 +113,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
} else {
// enables are all active high
cell->setPort(ceport, State::S1);
@ -165,7 +165,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP)));
}
log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
@ -183,7 +183,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
P.append(pm.module->addWire(NEWER_ID, 48 - GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
@ -214,12 +214,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEWER_ID, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(ID::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEWER_ID, arst));
} else {
// active low async/sync rst
cell->setPort(rstport, State::S1);
@ -229,7 +229,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
} else {
// enables are all active high
cell->setPort(ceport, State::S1);

2
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -112,7 +112,7 @@ finally
// Chain length exceeds the maximum cascade length, must split it up
if (i % MAX_DSP_CASCADE > 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEWER_ID, 48);
// zero port C and move wire to cascade
dsp_pcin->setPort(ID(C), Const(0, 48));

8
techlibs/nanoxplore/nx_carry.cc
View file

@ -81,7 +81,7 @@ static void nx_carry_chain(Module *module)
IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
cell = module->addCell(NEW_ID, ID(NX_CY));
cell = module->addCell(NEWER_ID, ID(NX_CY));
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(ID(CI), State::S1);
@ -92,7 +92,7 @@ static void nx_carry_chain(Module *module)
for (size_t i=0 ; i<c.second.size(); i++) {
if (j==0) {
cell = module->addCell(NEW_ID, ID(NX_CY));
cell = module->addCell(NEWER_ID, ID(NX_CY));
SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
cell->setPort(ID(CI), ci);
if (ci.is_wire()) {
@ -106,11 +106,11 @@ static void nx_carry_chain(Module *module)
}
if (j==3) {
if (cnt !=0 && (cnt % 24 == 0)) {
SigBit new_co = module->addWire(NEW_ID);
SigBit new_co = module->addWire(NEWER_ID);
cell->setPort(ID(A4), State::S0);
cell->setPort(ID(B4), State::S0);
cell->setPort(ID(S4), new_co);
cell = module->addCell(NEW_ID, ID(NX_CY));
cell = module->addCell(NEWER_ID, ID(NX_CY));
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(ID(CI), State::S1);
cell->setPort(ID(A1), new_co);

2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -127,7 +127,7 @@ struct QlBramMergeWorker {
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
RTLIL::Cell* merged = module->addCell(NEWER_ID, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
for (auto &it : param_map(false))

10
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -80,7 +80,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
log(" %s (%s)\n", log_id(cell), log_id(cell->type));
// Add the DSP cell
RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
RTLIL::Cell *cell = pm.module->addCell(NEWER_ID, type);
// Set attributes
cell->set_bool_attribute(ID(is_inferred), true);
@ -102,7 +102,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Connect output data port, pad if needed
if ((size_t) GetSize(sig_z) < tgt_z_width) {
auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
auto *wire = pm.module->addWire(NEWER_ID, tgt_z_width - GetSize(sig_z));
sig_z.append(wire);
}
cell->setPort(ID(z_o), sig_z);
@ -115,7 +115,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
if (st.ff->hasPort(ID(ARST))) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
rst = pm.module->Not(NEWER_ID, st.ff->getPort(ID(ARST)));
} else {
rst = st.ff->getPort(ID(ARST));
}
@ -125,7 +125,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
if (st.ff->hasPort(ID(EN))) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
ena = pm.module->Not(NEWER_ID, st.ff->getPort(ID(EN)));
} else {
ena = st.ff->getPort(ID(EN));
}
@ -143,7 +143,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Depending on the mux port ordering insert inverter if needed
log_assert(st.mux_ab.in(ID(A), ID(B)));
if (st.mux_ab == ID(A))
sig_s = pm.module->Not(NEW_ID, sig_s);
sig_s = pm.module->Not(NEWER_ID, sig_s);
// Assemble the full control signal for the feedback_i port
RTLIL::SigSpec sig_f;

4
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -148,7 +148,7 @@ struct QlDspSimdPass : public Pass {
Cell *dsp_b = group[i + 1];
// Create the new cell
Cell *simd = module->addCell(NEW_ID, m_SimdDspType);
Cell *simd = module->addCell(NEWER_ID, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type),
log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type));
@ -182,7 +182,7 @@ struct QlDspSimdPass : public Pass {
if (!isOutput)
sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding));
else
sigspec.append(module->addWire(NEW_ID, padding));
sigspec.append(module->addWire(NEWER_ID, padding));
}
return sigspec;
};

4
techlibs/quicklogic/ql_ioff.cc
View file

@ -91,7 +91,7 @@ struct QlIoffPass : public Pass {
if (std::any_of(ioff_cells.begin(), ioff_cells.end(), [](Cell * c) { return c != nullptr; }))
{
// create replacement output wire
RTLIL::Wire* new_port_output = module->addWire(NEW_ID, old_port_output->width);
RTLIL::Wire* new_port_output = module->addWire(NEWER_ID, old_port_output->width);
new_port_output->start_offset = old_port_output->start_offset;
module->swap_names(old_port_output, new_port_output);
std::swap(old_port_output->port_id, new_port_output->port_id);
@ -108,7 +108,7 @@ struct QlIoffPass : public Pass {
if (ioff_cells[i]) {
log("Promoting %s to output IOFF.\n", log_signal(sig_n[i]));
RTLIL::Cell *new_cell = module->addCell(NEW_ID, ID(dff));
RTLIL::Cell *new_cell = module->addCell(NEWER_ID, ID(dff));
new_cell->setPort(ID::C, ioff_cells[i]->getPort(ID::C));
new_cell->setPort(ID::D, ioff_cells[i]->getPort(ID::D));
new_cell->setPort(ID::Q, sig_n[i]);

14
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -323,28 +323,28 @@ unmap:
Cell *lut_cell = 0;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_ID, ID(LUT1));
lut_cell = module->addCell(NEWER_ID, ID(LUT1));
break;
case 2:
lut_cell = module->addCell(NEW_ID, ID(LUT2));
lut_cell = module->addCell(NEWER_ID, ID(LUT2));
break;
case 3:
lut_cell = module->addCell(NEW_ID, ID(LUT3));
lut_cell = module->addCell(NEWER_ID, ID(LUT3));
break;
case 4:
lut_cell = module->addCell(NEW_ID, ID(LUT4));
lut_cell = module->addCell(NEWER_ID, ID(LUT4));
break;
case 5:
lut_cell = module->addCell(NEW_ID, ID(LUT5));
lut_cell = module->addCell(NEWER_ID, ID(LUT5));
break;
case 6:
lut_cell = module->addCell(NEW_ID, ID(LUT6));
lut_cell = module->addCell(NEWER_ID, ID(LUT6));
break;
default:
log_assert(!"unknown lut size");
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
Wire *lut_out = module->addWire(NEWER_ID);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::O, lut_out);

42
techlibs/xilinx/xilinx_dsp.cc
View file

@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
#include "techlibs/xilinx/xilinx_dsp_cascade_pm.h"
static Cell* addDsp(Module *module) {
Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));
Cell *cell = module->addCell(NEWER_ID, ID(DSP48E1));
cell->setParam(ID(ACASCREG), 0);
cell->setParam(ID(ADREG), 0);
cell->setParam(ID(A_INPUT), Const("DIRECT"));
@ -114,7 +114,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
AB.append(A);
C.append(B);
if (GetSize(Y) < 13)
Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
Y.append(module->addWire(NEWER_ID, 13-GetSize(Y)));
else
log_assert(GetSize(Y) == 13);
P.append(Y.extract(0, 12));
@ -160,15 +160,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
else {
AB.append(Const(0, 12));
C.append(Const(0, 12));
P.append(module->addWire(NEW_ID, 12));
CARRYOUT.append(module->addWire(NEW_ID, 1));
P.append(module->addWire(NEWER_ID, 12));
CARRYOUT.append(module->addWire(NEWER_ID, 1));
}
}
else {
AB.append(Const(0, 24));
C.append(Const(0, 24));
P.append(module->addWire(NEW_ID, 24));
CARRYOUT.append(module->addWire(NEW_ID, 2));
P.append(module->addWire(NEWER_ID, 24));
CARRYOUT.append(module->addWire(NEWER_ID, 2));
}
log_assert(GetSize(AB) == 48);
log_assert(GetSize(C) == 48);
@ -202,11 +202,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
C.append(A);
AB.append(B);
if (GetSize(Y) < 25)
Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
Y.append(module->addWire(NEWER_ID, 25-GetSize(Y)));
else
log_assert(GetSize(Y) == 25);
P.append(Y.extract(0, 24));
CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit
CARRYOUT.append(module->addWire(NEWER_ID)); // TWO24 uses every other bit
CARRYOUT.append(Y[24]);
};
auto g24 = [&f24,module](std::deque<Cell*> &simd24) {
@ -294,7 +294,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(ID::EN);
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEWER_ID, S));
}
else
cell->setPort(ID(CEAD), State::S1);
@ -373,7 +373,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -381,7 +381,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);
@ -437,13 +437,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -477,7 +477,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
@ -560,7 +560,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -568,7 +568,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);
@ -620,13 +620,13 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -655,7 +655,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
@ -683,7 +683,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -691,7 +691,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);

6
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -89,7 +89,7 @@ finally
if (i % MAX_DSP_CASCADE > 0) {
if (P >= 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEWER_ID, 48);
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(PCIN), cascade);
dsp->setPort(ID(PCOUT), cascade);
@ -117,7 +117,7 @@ finally
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
Wire *cascade = module->addWire(NEWER_ID, 30);
dsp_pcin->setPort(ID(A), Const(0, 30));
dsp_pcin->setPort(ID(ACIN), cascade);
dsp->setPort(ID(ACOUT), cascade);
@ -131,7 +131,7 @@ finally
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
}
if (BREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 18);
Wire *cascade = module->addWire(NEWER_ID, 18);
if (dsp->type.in(\DSP48A, \DSP48A1)) {
// According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
// "The DSP48A1 component uses this input when cascading

4
techlibs/xilinx/xilinx_srl.cc
View file

@ -59,7 +59,7 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
@ -134,7 +134,7 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {

44
techlibs/xilinx/xilinx_srl.pmg
View file

@ -18,22 +18,22 @@ match first
select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
filter !non_first_cells.count(first)
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec D = module->addWire(NEW_ID);
SigSpec Q = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
SigSpec D = module->addWire(NEWER_ID);
SigSpec Q = module->addWire(NEWER_ID);
auto r = rng(8);
Cell* cell;
switch (r)
{
case 0:
case 1:
cell = module->addCell(NEW_ID, \FDRE);
cell = module->addCell(NEWER_ID, \FDRE);
cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
cell->setPort(\CE, module->addWire(NEW_ID));
cell->setPort(\CE, module->addWire(NEWER_ID));
if (r & 1)
cell->setPort(\R, module->addWire(NEW_ID));
cell->setPort(\R, module->addWire(NEWER_ID));
else {
if (rng(2) == 0)
cell->setPort(\R, State::S0);
@ -41,13 +41,13 @@ generate
break;
case 2:
case 3:
cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
cell = module->addDffGate(NEWER_ID, C, D, Q, r & 1);
break;
case 4:
case 5:
case 6:
case 7:
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
cell = module->addDffeGate(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 2);
break;
default: log_abort();
}
@ -143,9 +143,9 @@ match next
filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type);
Cell *cell = module->addCell(NEWER_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, chain.back()->getPort(\D));
if (cell->type == \FDRE) {
if (rng(2) == 0)
@ -191,7 +191,7 @@ match shiftx
filter param(shiftx, \A_WIDTH).as_int() >= minlen
generate
minlen = 3;
module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
module->addShiftx(NEWER_ID, module->addWire(NEWER_ID, rng(6)+minlen), module->addWire(NEWER_ID, 3), module->addWire(NEWER_ID));
endmatch
code shiftx_width
@ -207,28 +207,28 @@ match first
index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
set slice idx
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
auto WIDTH = rng(3)+1;
SigSpec D = module->addWire(NEW_ID, WIDTH);
SigSpec Q = module->addWire(NEW_ID, WIDTH);
SigSpec D = module->addWire(NEWER_ID, WIDTH);
SigSpec Q = module->addWire(NEWER_ID, WIDTH);
auto r = rng(8);
Cell *cell = nullptr;
switch (r)
{
case 0:
case 1:
cell = module->addDff(NEW_ID, C, D, Q, r & 1);
cell = module->addDff(NEWER_ID, C, D, Q, r & 1);
break;
case 2:
case 3:
case 4:
case 5:
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
//cell = module->addDffe(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 4);
//break;
case 6:
case 7:
WIDTH = 1;
cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
cell = module->addDffGate(NEWER_ID, C, D[0], Q[0], r & 1);
break;
default: log_abort();
}
@ -295,19 +295,19 @@ generate
back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
}
else {
auto D = module->addWire(NEW_ID, WIDTH);
auto D = module->addWire(NEWER_ID, WIDTH);
if (back->type == $dff)
module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
module->addDff(NEWER_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
else if (back->type == $dffe)
module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
module->addDffe(NEWER_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
else
log_abort();
}
}
else if (back->type.begins_with("$_DFF_")) {
Cell *cell = module->addCell(NEW_ID, back->type);
Cell *cell = module->addCell(NEWER_ID, back->type);
cell->setPort(\C, back->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, back->getPort(\D));
}
else