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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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6
passes/techmap/clockgate.cc
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@ -371,17 +371,17 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
Cell* icg = module->addCell(NEWER_ID, matching_icg_desc->name);
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
gclk.new_net = module->addWire(NEW_ID);
gclk.new_net = module->addWire(NEWER_ID);
icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
// Tie low DFT ports like scan chain enable
for (auto port : matching_icg_desc->tie_lo_pins)
icg->setPort(port, Const(0, 1));
// Fix CE polarity if needed
if (!clk.pol_ce) {
SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
SigBit ce_fixed_pol = module->NotGate(NEWER_ID, clk.ce_bit);
icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
}
}