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https://github.com/YosysHQ/yosys
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s/NEW_ID/NEWER_ID/g
This commit is contained in:
Emil J. Tywoniak
parent
6b9082fa64
commit
73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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@ -75,44 +75,44 @@ struct BoothPassWorker {
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// Booth unsigned decoder lsb
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SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
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{
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SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i);
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return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i);
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SigBit and_op = module->AndGate(NEWER_ID_SUFFIX(name), lsb_i, one_i);
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return module->XorGate(NEWER_ID_SUFFIX(name), and_op, s_i);
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}
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// Booth unsigned radix4 decoder
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SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i)
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{
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// ppij = ((yn & one) | (ynm1 & two)) ^ s;
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SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i);
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SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i);
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SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2);
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return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1);
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SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), yn_i, one_i);
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SigBit an2 = module->AndGate(NEWER_ID_SUFFIX(name), ynm1_i, two_i);
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SigBit or1 = module->OrGate(NEWER_ID_SUFFIX(name), an1, an2);
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return module->XorGate(NEWER_ID_SUFFIX(name), s_i, or1);
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}
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// Booth unsigned radix4 decoder
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SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i)
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{
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// ppij = (msb & two) ^ s;
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SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i);
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return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1);
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SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), msb_i, two_i);
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return module->XorGate(NEWER_ID_SUFFIX(name), s_i, an1);
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}
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// half adder, used in CPA
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void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o)
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{
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s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i);
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c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i);
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s_o = module->XorGate(NEWER_ID_SUFFIX(name), a_i, b_i);
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c_o = module->AndGate(NEWER_ID_SUFFIX(name), a_i, b_i);
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}
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// Booth unsigned radix 4 encoder
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void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i,
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SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o)
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{
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one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i);
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one_o = module->XorGate(NEWER_ID_SUFFIX(name), y0_i, y1_i);
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s_o = y2_i;
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sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
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SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i);
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two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o);
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sb_o = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
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SigBit y1_xnor_y2 = module->XnorGate(NEWER_ID_SUFFIX(name), y1_i, y2_i);
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two_o = module->NorGate(NEWER_ID_SUFFIX(name), y1_xnor_y2, one_o);
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}
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void BuildBr4e(std::string name, SigBit y2_m1_i,
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@ -120,9 +120,9 @@ struct BoothPassWorker {
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SigBit y2_p1_i,
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SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o)
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{
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auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i);
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auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
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auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i);
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auto y2_p1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_p1_i);
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auto y2_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
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auto y2_m1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_m1_i);
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negi_o = y2_p1_i;
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@ -130,15 +130,15 @@ struct BoothPassWorker {
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// (y2_p1_n & y2_i & y2_m1_i) |
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// (y2_p1 & y2_n & y2_m1_n)
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// )
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twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name),
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module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)),
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module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n))
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twoi_n_o = module->NorGate(NEWER_ID_SUFFIX(name),
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module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEWER_ID_SUFFIX(name), y2_i, y2_m1_i)),
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module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEWER_ID_SUFFIX(name), y2_n, y2_m1_n))
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);
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// onei_n = ~(y2_m1_i ^ y2_i);
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onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i);
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onei_n_o = module->XnorGate(NEWER_ID_SUFFIX(name), y2_m1_i, y2_i);
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// cori = (y2_m1_n | y2_n) & y2_p1_i;
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cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
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cori_o = module->AndGate(NEWER_ID_SUFFIX(name), module->OrGate(NEWER_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
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}
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//
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@ -150,10 +150,10 @@ struct BoothPassWorker {
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// nxj_in = xnor(xj,negi)
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// nxj_o = xnj_in,
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// ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i));
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nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i);
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ppij_o = module->NandGate(NEW_ID_SUFFIX(name),
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module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
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module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i)
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nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), xj_i, negi_i);
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ppij_o = module->NandGate(NEWER_ID_SUFFIX(name),
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module->OrGate(NEWER_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
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module->OrGate(NEWER_ID_SUFFIX(name), nxj_o, onei_n_i)
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);
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}
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@ -177,14 +177,14 @@ struct BoothPassWorker {
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//correction propagation
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assign CORO = (~PP1 & ~PP0)? CORI : 1'b0;
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*/
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nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i);
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pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i);
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SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i);
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SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i);
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pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
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nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), x1_i, negi_i);
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pp0_o = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y0_i);
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SigBit pp1_1_int = module->AndGate(NEWER_ID_SUFFIX(name), x1_i, y0_i);
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SigBit pp1_2_int = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y1_i);
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pp1_o = module->XorGate(NEWER_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
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SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o);
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cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
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SigBit pp1_nor_pp0 = module->NorGate(NEWER_ID_SUFFIX(name), pp1_o, pp0_o);
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cor_o = module->AndGate(NEWER_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
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}
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void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b,
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@ -289,7 +289,7 @@ struct BoothPassWorker {
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int required_op_size = x_sz_revised + y_sz_revised;
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if (required_op_size != z_sz) {
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SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
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SigSpec expanded_Y = module->addWire(NEWER_ID, required_op_size);
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SigSpec Y_driver = expanded_Y;
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Y_driver.extend_u0(Y.size(), is_signed);
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module->connect(Y, Y_driver);
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@ -326,9 +326,9 @@ struct BoothPassWorker {
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std::vector<SigSpec> new_summands;
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int i;
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for (i = 0; i < (int) summands.size() - 2; i += 3) {
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SigSpec x = module->addWire(NEW_ID, width);
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SigSpec y = module->addWire(NEW_ID, width);
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BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1],
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SigSpec x = module->addWire(NEWER_ID, width);
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SigSpec y = module->addWire(NEWER_ID, width);
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BuildBitwiseFa(module, NEWER_ID.str(), summands[i], summands[i + 1],
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summands[i + 2], x, y);
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new_summands.push_back(y);
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new_summands.push_back({x.extract(0, width - 1), State::S0});
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@ -424,7 +424,7 @@ struct BoothPassWorker {
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if (mapped_cpa)
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BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z);
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else
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module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
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module->addAdd(NEWER_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
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}
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/*
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@ -460,11 +460,11 @@ struct BoothPassWorker {
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// append the sign bits
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if (is_signed) {
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SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0])));
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ppij_vec.append({module->NotGate(NEW_ID, e), e, e});
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SigBit e = module->XorGate(NEWER_ID, s_int[0], module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int[0], one_int[0])));
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ppij_vec.append({module->NotGate(NEWER_ID, e), e, e});
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} else {
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// append the sign bits
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ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]});
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ppij_vec.append({module->NotGate(NEWER_ID, s_int[0]), s_int[0], s_int[0]});
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}
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}
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@ -494,7 +494,7 @@ struct BoothPassWorker {
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one_int, two_int, s_int));
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}
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ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int))));
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ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEWER_ID, sb_int, module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int, one_int))));
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ppij_vec.append(State::S1);
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}
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@ -721,7 +721,7 @@ struct BoothPassWorker {
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// Base Case: Bit 0 is sum 0
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if (n == 0) {
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module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
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module->addBufGate(NEWER_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
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#ifdef DEBUG_CPA
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printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str());
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@ -747,8 +747,8 @@ struct BoothPassWorker {
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// End Case
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else if (n == s_vec.size() - 1) {
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// Make the carry results.. Two extra bits after fa.
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SigBit carry_out = module->addWire(NEW_ID, 1);
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module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
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SigBit carry_out = module->addWire(NEWER_ID, 1);
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module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
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/* A */ s_vec[n],
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/* B */ c_vec[n - 1],
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/* C */ carry,
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@ -775,8 +775,8 @@ struct BoothPassWorker {
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}
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// Step case
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else {
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SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
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module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
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SigBit carry_out = module->addWire(NEWER_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
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module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
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/* A */ s_vec[n],
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/* B */ c_vec[n - 1],
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/* C */ carry,
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@ -814,10 +814,10 @@ struct BoothPassWorker {
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if (first_csa_ips.size() > 0) {
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// build the first csa
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auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
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auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
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auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
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auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
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auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
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auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
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/* A */ first_csa_ips[0],
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/* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0,
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/* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0,
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@ -846,10 +846,10 @@ struct BoothPassWorker {
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}
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if (csa_ips.size() > 0) {
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auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
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auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
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auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
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auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
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auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
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auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
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/* A */ s_result,
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/* B */ csa_ips[0],
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/* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0,
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@ -879,10 +879,10 @@ struct BoothPassWorker {
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for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) {
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std::string enc_name = stringf("bur_enc_%d", encoder_ix);
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two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
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one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
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s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
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sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
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two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
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one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
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s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
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sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
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if (y_ix == 0) {
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BuildBur4e(enc_name, State::S0, Y[y_ix],
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@ -939,10 +939,10 @@ struct BoothPassWorker {
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std::string enc_name = stringf("br_enc_pad_%d", encoder_ix);
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two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
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one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
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s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
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sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
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two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
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one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
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s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
|
||||
sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
|
||||
|
||||
SigBit one_o_int, two_o_int, s_o_int, sb_o_int;
|
||||
BuildBur4e(enc_name, Y[y_ix], State::S0,
|
||||
|
|
@ -986,10 +986,10 @@ struct BoothPassWorker {
|
|||
|
||||
for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) {
|
||||
std::string enc_name = stringf("enc_%d", encoder_ix);
|
||||
negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
|
||||
twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
|
||||
onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
|
||||
cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
|
||||
negi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
|
||||
twoi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
|
||||
onei_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
|
||||
cori_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
|
||||
|
||||
if (encoder_ix == 1) {
|
||||
BuildBr4e(enc_name, State::S0, Y[0], Y[1],
|
||||
|
|
@ -1024,10 +1024,10 @@ struct BoothPassWorker {
|
|||
for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
|
||||
for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) {
|
||||
PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
|
||||
module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
|
||||
module->addWire(NEWER_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
|
||||
|
||||
nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
|
||||
module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
|
||||
module->addWire(NEWER_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
|
||||
encoder_ix, decoder_ix)), 1);
|
||||
}
|
||||
}
|
||||
|
|
@ -1042,7 +1042,7 @@ struct BoothPassWorker {
|
|||
if (encoder_ix == 1) {
|
||||
// quadrant 1 optimization
|
||||
} else {
|
||||
module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
|
||||
module->addNotGate(NEWER_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
|
||||
negi_n_int[encoder_ix - 1],
|
||||
nxj[(encoder_ix - 1) * dec_count]
|
||||
);
|
||||
|
|
@ -1094,16 +1094,16 @@ struct BoothPassWorker {
|
|||
std::vector<SigSpec> fa_carry;
|
||||
|
||||
for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) {
|
||||
fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
|
||||
fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
|
||||
fa_sum.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
|
||||
fa_carry.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
|
||||
}
|
||||
|
||||
// full adder creation
|
||||
// base case: 1st row: Inputs from decoders
|
||||
// 1st row exception: two localized inverters due to sign extension structure
|
||||
SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
|
||||
SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
|
||||
BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(),
|
||||
SigBit d08_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
|
||||
SigBit d18_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
|
||||
BuildBitwiseFa(module, NEWER_ID_SUFFIX("fa_row_0").str(),
|
||||
/* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)},
|
||||
/* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)},
|
||||
/* C */ fa_carry[0].extract(1, x_sz + 2),
|
||||
|
|
@ -1116,10 +1116,10 @@ struct BoothPassWorker {
|
|||
// special because these are driven by a decoder and prior fa.
|
||||
for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) {
|
||||
// end two bits: sign extension
|
||||
SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
|
||||
SigBit d_inv = module->NotGate(NEWER_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
|
||||
PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
|
||||
|
||||
BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
|
||||
BuildBitwiseFa(module, NEWER_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
|
||||
/* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)},
|
||||
/* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0},
|
||||
|
||||
|
|
@ -1132,7 +1132,7 @@ struct BoothPassWorker {
|
|||
// instantiate the cpa
|
||||
SigSpec cpa_carry;
|
||||
if (z_sz > fa_row_count * 2)
|
||||
cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
|
||||
cpa_carry = module->addWire(NEWER_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
|
||||
|
||||
// The end case where we pass the last two summands
|
||||
// from prior row directly to product output
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue