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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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24
passes/techmap/abc9_ops.cc
View file

@ -344,7 +344,7 @@ void prep_bypass(RTLIL::Design *design)
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
auto specify = bypass_module->addCell(NEWER_ID, ID($specify2));
specify->setPort(ID::EN, State::S1);
specify->setPort(ID::SRC, src);
specify->setPort(ID::DST, dst);
@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design)
}
sig = std::move(new_sig);
};
auto specify = bypass_module->addCell(NEW_ID, cell);
auto specify = bypass_module->addCell(NEWER_ID, cell);
specify->rewrite_sigspecs(rw);
}
bypass_module->fixup_ports();
@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design)
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
auto bypass_cell = map_module->addCell(NEWER_ID, cell->type.str() + "_$abc9_byp");
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
if (cell->input(conn.first)) {
@ -503,8 +503,8 @@ void prep_dff_submod(RTLIL::Design *design)
// Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that:
// (a) flop box will have an output
// (b) $_DFF_[NP]_.Q will be present as an input
SigBit D = module->addWire(NEW_ID);
module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
SigBit D = module->addWire(NEWER_ID);
module->addMuxGate(NEWER_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
dff_cell->setPort(ID::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
@ -592,7 +592,7 @@ void break_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEWER_ID, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -602,7 +602,7 @@ void break_scc(RTLIL::Module *module)
if (!I.empty())
{
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEWER_ID, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
@ -680,7 +680,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto rhs = cell->getPort(i.first.name);
if (offset >= rhs.size())
continue;
auto O = module->addWire(NEW_ID);
auto O = module->addWire(NEWER_ID);
#ifndef NDEBUG
if (ys_debug(1)) {
@ -694,7 +694,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
auto box = module->addCell(NEWER_ID, r.first->second);
box->setPort(ID::I, rhs[offset]);
box->setPort(ID::O, O);
rhs[offset] = O;
@ -831,7 +831,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(NEW_ID, cell->type);
holes_cell = holes_module->addCell(NEWER_ID, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc -noopt");
@ -1256,7 +1256,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
mapped_cell->setPort(ID::Y, module->addWire(NEWER_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -1549,7 +1549,7 @@ clone_lut:
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
auto cell = module->addLut(NEWER_ID,
driver_lut->getPort(ID::A),
y_bit,
driver_mask);

12
passes/techmap/aigmap.cc
View file

@ -108,8 +108,8 @@ struct AigmapPass : public Pass {
SigBit A = sigs.at(node.left_parent);
SigBit B = sigs.at(node.right_parent);
if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID);
auto gate = module->addNandGate(NEW_ID, A, B, bit);
bit = module->addWire(NEWER_ID);
auto gate = module->addNandGate(NEWER_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
@ -119,8 +119,8 @@ struct AigmapPass : public Pass {
if (and_cache.count(key))
bit = and_cache.at(key);
else {
bit = module->addWire(NEW_ID);
auto gate = module->addAndGate(NEW_ID, A, B, bit);
bit = module->addWire(NEWER_ID);
auto gate = module->addAndGate(NEWER_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
}
@ -128,8 +128,8 @@ struct AigmapPass : public Pass {
}
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID);
auto gate = module->addNotGate(NEW_ID, bit, new_bit);
SigBit new_bit = module->addWire(NEWER_ID);
auto gate = module->addNotGate(NEWER_ID, bit, new_bit);
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);

28
passes/techmap/alumacc.cc
View file

@ -52,7 +52,7 @@ struct AlumaccWorker
if (is_signed) {
get_of();
get_sf();
cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
cached_lt = alu_cell->module->Xor(NEWER_ID, cached_of, cached_sf);
}
else
cached_lt = get_cf();
@ -64,21 +64,21 @@ struct AlumaccWorker
if (GetSize(cached_gt) == 0) {
get_lt();
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
SigSpec Or = alu_cell->module->Or(NEWER_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEWER_ID, Or, false, alu_cell->get_src_attribute());
}
return cached_gt;
}
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
cached_eq = alu_cell->module->ReduceAnd(NEWER_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
cached_ne = alu_cell->module->Not(NEWER_ID, get_eq(), false, alu_cell->get_src_attribute());
return cached_ne;
}
@ -86,7 +86,7 @@ struct AlumaccWorker
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
cached_cf = alu_cell->module->Not(NEWER_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
}
return cached_cf;
}
@ -95,7 +95,7 @@ struct AlumaccWorker
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
cached_of = alu_cell->module->Xor(NEWER_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
return cached_of;
}
@ -362,7 +362,7 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
auto cell = module->addCell(NEW_ID, ID($macc));
auto cell = module->addCell(NEWER_ID, ID($macc));
macc_counter++;
@ -428,7 +428,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEWER_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
@ -482,7 +482,7 @@ struct AlumaccWorker
{
if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
n->alu_cell = module->addPos(NEWER_ID, n->a, n->y, n->is_signed);
log(" creating $pos cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
@ -492,7 +492,7 @@ struct AlumaccWorker
goto delete_node;
}
n->alu_cell = module->addCell(NEW_ID, ID($alu));
n->alu_cell = module->addCell(NEWER_ID, ID($alu));
alu_counter++;
log(" creating $alu cell for ");
@ -508,8 +508,8 @@ struct AlumaccWorker
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::X, module->addWire(NEWER_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEWER_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
@ -527,7 +527,7 @@ struct AlumaccWorker
if (cmp_ne) sig.append(n->get_ne());
if (GetSize(sig) > 1)
sig = module->ReduceOr(NEW_ID, sig);
sig = module->ReduceOr(NEWER_ID, sig);
sig.extend_u0(GetSize(cmp_y));
module->connect(cmp_y, sig);

12
passes/techmap/bmuxmap.cc
View file

@ -68,22 +68,22 @@ struct BmuxmapPass : public Pass {
{
int num_cases = 1 << s_width;
SigSpec new_a = SigSpec(State::Sx, width);
SigSpec new_s = module->addWire(NEW_ID, num_cases);
SigSpec new_data = module->addWire(NEW_ID, width);
SigSpec new_s = module->addWire(NEWER_ID, num_cases);
SigSpec new_data = module->addWire(NEWER_ID, width);
for (int val = 0; val < num_cases; val++)
{
module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
module->addEq(NEWER_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
}
RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
RTLIL::Cell *pmux = module->addPmux(NEWER_ID, new_a, data, new_s, new_data);
pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
data = new_data;
}
else
{
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
RTLIL::Cell *mux = module->addMux(NEW_ID,
RTLIL::Cell *mux = module->addMux(NEWER_ID,
data.extract(i*2, width),
data.extract(i*2+width, width),
sel[idx],

152
passes/techmap/booth.cc
View file

@ -75,44 +75,44 @@ struct BoothPassWorker {
// Booth unsigned decoder lsb
SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
{
SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i);
return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i);
SigBit and_op = module->AndGate(NEWER_ID_SUFFIX(name), lsb_i, one_i);
return module->XorGate(NEWER_ID_SUFFIX(name), and_op, s_i);
}
// Booth unsigned radix4 decoder
SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i)
{
// ppij = ((yn & one) | (ynm1 & two)) ^ s;
SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i);
SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i);
SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2);
return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1);
SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), yn_i, one_i);
SigBit an2 = module->AndGate(NEWER_ID_SUFFIX(name), ynm1_i, two_i);
SigBit or1 = module->OrGate(NEWER_ID_SUFFIX(name), an1, an2);
return module->XorGate(NEWER_ID_SUFFIX(name), s_i, or1);
}
// Booth unsigned radix4 decoder
SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i)
{
// ppij = (msb & two) ^ s;
SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i);
return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1);
SigBit an1 = module->AndGate(NEWER_ID_SUFFIX(name), msb_i, two_i);
return module->XorGate(NEWER_ID_SUFFIX(name), s_i, an1);
}
// half adder, used in CPA
void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o)
{
s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i);
c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i);
s_o = module->XorGate(NEWER_ID_SUFFIX(name), a_i, b_i);
c_o = module->AndGate(NEWER_ID_SUFFIX(name), a_i, b_i);
}
// Booth unsigned radix 4 encoder
void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i,
SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o)
{
one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i);
one_o = module->XorGate(NEWER_ID_SUFFIX(name), y0_i, y1_i);
s_o = y2_i;
sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i);
two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o);
sb_o = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
SigBit y1_xnor_y2 = module->XnorGate(NEWER_ID_SUFFIX(name), y1_i, y2_i);
two_o = module->NorGate(NEWER_ID_SUFFIX(name), y1_xnor_y2, one_o);
}
void BuildBr4e(std::string name, SigBit y2_m1_i,
@ -120,9 +120,9 @@ struct BoothPassWorker {
SigBit y2_p1_i,
SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o)
{
auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i);
auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i);
auto y2_p1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_p1_i);
auto y2_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_i);
auto y2_m1_n = module->NotGate(NEWER_ID_SUFFIX(name), y2_m1_i);
negi_o = y2_p1_i;
@ -130,15 +130,15 @@ struct BoothPassWorker {
// (y2_p1_n & y2_i & y2_m1_i) |
// (y2_p1 & y2_n & y2_m1_n)
// )
twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n))
twoi_n_o = module->NorGate(NEWER_ID_SUFFIX(name),
module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEWER_ID_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEWER_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEWER_ID_SUFFIX(name), y2_n, y2_m1_n))
);
// onei_n = ~(y2_m1_i ^ y2_i);
onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i);
onei_n_o = module->XnorGate(NEWER_ID_SUFFIX(name), y2_m1_i, y2_i);
// cori = (y2_m1_n | y2_n) & y2_p1_i;
cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
cori_o = module->AndGate(NEWER_ID_SUFFIX(name), module->OrGate(NEWER_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
}
//
@ -150,10 +150,10 @@ struct BoothPassWorker {
// nxj_in = xnor(xj,negi)
// nxj_o = xnj_in,
// ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i));
nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i);
ppij_o = module->NandGate(NEW_ID_SUFFIX(name),
module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i)
nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), xj_i, negi_i);
ppij_o = module->NandGate(NEWER_ID_SUFFIX(name),
module->OrGate(NEWER_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
module->OrGate(NEWER_ID_SUFFIX(name), nxj_o, onei_n_i)
);
}
@ -177,14 +177,14 @@ struct BoothPassWorker {
//correction propagation
assign CORO = (~PP1 & ~PP0)? CORI : 1'b0;
*/
nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i);
pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i);
SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i);
SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i);
pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
nxj_o = module->XnorGate(NEWER_ID_SUFFIX(name), x1_i, negi_i);
pp0_o = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y0_i);
SigBit pp1_1_int = module->AndGate(NEWER_ID_SUFFIX(name), x1_i, y0_i);
SigBit pp1_2_int = module->AndGate(NEWER_ID_SUFFIX(name), x0_i, y1_i);
pp1_o = module->XorGate(NEWER_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o);
cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
SigBit pp1_nor_pp0 = module->NorGate(NEWER_ID_SUFFIX(name), pp1_o, pp0_o);
cor_o = module->AndGate(NEWER_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
}
void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b,
@ -289,7 +289,7 @@ struct BoothPassWorker {
int required_op_size = x_sz_revised + y_sz_revised;
if (required_op_size != z_sz) {
SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
SigSpec expanded_Y = module->addWire(NEWER_ID, required_op_size);
SigSpec Y_driver = expanded_Y;
Y_driver.extend_u0(Y.size(), is_signed);
module->connect(Y, Y_driver);
@ -326,9 +326,9 @@ struct BoothPassWorker {
std::vector<SigSpec> new_summands;
int i;
for (i = 0; i < (int) summands.size() - 2; i += 3) {
SigSpec x = module->addWire(NEW_ID, width);
SigSpec y = module->addWire(NEW_ID, width);
BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1],
SigSpec x = module->addWire(NEWER_ID, width);
SigSpec y = module->addWire(NEWER_ID, width);
BuildBitwiseFa(module, NEWER_ID.str(), summands[i], summands[i + 1],
summands[i + 2], x, y);
new_summands.push_back(y);
new_summands.push_back({x.extract(0, width - 1), State::S0});
@ -424,7 +424,7 @@ struct BoothPassWorker {
if (mapped_cpa)
BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z);
else
module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
module->addAdd(NEWER_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
}
/*
@ -460,11 +460,11 @@ struct BoothPassWorker {
// append the sign bits
if (is_signed) {
SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEW_ID, e), e, e});
SigBit e = module->XorGate(NEWER_ID, s_int[0], module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEWER_ID, e), e, e});
} else {
// append the sign bits
ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]});
ppij_vec.append({module->NotGate(NEWER_ID, s_int[0]), s_int[0], s_int[0]});
}
}
@ -494,7 +494,7 @@ struct BoothPassWorker {
one_int, two_int, s_int));
}
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int))));
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEWER_ID, sb_int, module->AndGate(NEWER_ID, X.msb(), module->OrGate(NEWER_ID, two_int, one_int))));
ppij_vec.append(State::S1);
}
@ -721,7 +721,7 @@ struct BoothPassWorker {
// Base Case: Bit 0 is sum 0
if (n == 0) {
module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
module->addBufGate(NEWER_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str());
@ -747,8 +747,8 @@ struct BoothPassWorker {
// End Case
else if (n == s_vec.size() - 1) {
// Make the carry results.. Two extra bits after fa.
SigBit carry_out = module->addWire(NEW_ID, 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
SigBit carry_out = module->addWire(NEWER_ID, 1);
module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
/* C */ carry,
@ -775,8 +775,8 @@ struct BoothPassWorker {
}
// Step case
else {
SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
SigBit carry_out = module->addWire(NEWER_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
module->addFa(NEWER_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
/* C */ carry,
@ -814,10 +814,10 @@ struct BoothPassWorker {
if (first_csa_ips.size() > 0) {
// build the first csa
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ first_csa_ips[0],
/* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0,
/* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0,
@ -846,10 +846,10 @@ struct BoothPassWorker {
}
if (csa_ips.size() > 0) {
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEWER_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
auto csa = module->addFa(NEWER_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ s_result,
/* B */ csa_ips[0],
/* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0,
@ -879,10 +879,10 @@ struct BoothPassWorker {
for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) {
std::string enc_name = stringf("bur_enc_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
if (y_ix == 0) {
BuildBur4e(enc_name, State::S0, Y[y_ix],
@ -939,10 +939,10 @@ struct BoothPassWorker {
std::string enc_name = stringf("br_enc_pad_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEWER_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
SigBit one_o_int, two_o_int, s_o_int, sb_o_int;
BuildBur4e(enc_name, Y[y_ix], State::S0,
@ -986,10 +986,10 @@ struct BoothPassWorker {
for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) {
std::string enc_name = stringf("enc_%d", encoder_ix);
negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
negi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEWER_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
if (encoder_ix == 1) {
BuildBr4e(enc_name, State::S0, Y[0], Y[1],
@ -1024,10 +1024,10 @@ struct BoothPassWorker {
for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) {
PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
module->addWire(NEWER_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
module->addWire(NEWER_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
encoder_ix, decoder_ix)), 1);
}
}
@ -1042,7 +1042,7 @@ struct BoothPassWorker {
if (encoder_ix == 1) {
// quadrant 1 optimization
} else {
module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
module->addNotGate(NEWER_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
negi_n_int[encoder_ix - 1],
nxj[(encoder_ix - 1) * dec_count]
);
@ -1094,16 +1094,16 @@ struct BoothPassWorker {
std::vector<SigSpec> fa_carry;
for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) {
fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
fa_sum.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEWER_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
}
// full adder creation
// base case: 1st row: Inputs from decoders
// 1st row exception: two localized inverters due to sign extension structure
SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(),
SigBit d08_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
SigBit d18_inv = module->NotGate(NEWER_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEWER_ID_SUFFIX("fa_row_0").str(),
/* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)},
/* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)},
/* C */ fa_carry[0].extract(1, x_sz + 2),
@ -1116,10 +1116,10 @@ struct BoothPassWorker {
// special because these are driven by a decoder and prior fa.
for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) {
// end two bits: sign extension
SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
SigBit d_inv = module->NotGate(NEWER_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
BuildBitwiseFa(module, NEWER_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
/* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)},
/* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0},
@ -1132,7 +1132,7 @@ struct BoothPassWorker {
// instantiate the cpa
SigSpec cpa_carry;
if (z_sz > fa_row_count * 2)
cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
cpa_carry = module->addWire(NEWER_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
// The end case where we pass the last two summands
// from prior row directly to product output

4
passes/techmap/bufnorm.cc
View file

@ -384,7 +384,7 @@ struct BufnormPass : public Pass {
it->second.sort(compare_wires_f);
w = *(it->second.begin());
} else {
w = module->addWire(NEW_ID, GetSize(conn.second));
w = module->addWire(NEWER_ID, GetSize(conn.second));
for (int i = 0; i < GetSize(w); i++)
sigmap.add(SigBit(w, i), keysig[i]);
}
@ -434,7 +434,7 @@ struct BufnormPass : public Pass {
return;
}
Cell *cell = module->addCell(NEW_ID, type);
Cell *cell = module->addCell(NEWER_ID, type);
added_buffers.insert(cell);
cell->setPort(ID::A, src);

8
passes/techmap/bwmuxmap.cc
View file

@ -57,10 +57,10 @@ struct BwmuxmapPass : public Pass {
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto not_s = module->Not(NEW_ID, sig_s);
auto masked_b = module->And(NEW_ID, sig_s, sig_b);
auto masked_a = module->And(NEW_ID, not_s, sig_a);
module->addOr(NEW_ID, masked_a, masked_b, sig_y);
auto not_s = module->Not(NEWER_ID, sig_s);
auto masked_b = module->And(NEWER_ID, sig_s, sig_b);
auto masked_a = module->And(NEWER_ID, not_s, sig_a);
module->addOr(NEWER_ID, masked_a, masked_b, sig_y);
module->remove(cell);
}

10
passes/techmap/clkbufmap.cc
View file

@ -258,21 +258,21 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell = module->addCell(NEWER_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEWER_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEWER_ID, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_ID);
iwire = module->addWire(NEWER_ID);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
}
if (iwire)
@ -291,7 +291,7 @@ struct ClkbufmapPass : public Pass {
if (!input_bits.empty()) {
// This is an input port and some buffers were inserted -- we need
// to create a new input wire and transfer attributes.
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEWER_ID, wire);
for (int i = 0; i < wire->width; i++) {
SigBit wire_bit(wire, i);

6
passes/techmap/clockgate.cc
View file

@ -371,17 +371,17 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
Cell* icg = module->addCell(NEWER_ID, matching_icg_desc->name);
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
gclk.new_net = module->addWire(NEW_ID);
gclk.new_net = module->addWire(NEWER_ID);
icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
// Tie low DFT ports like scan chain enable
for (auto port : matching_icg_desc->tie_lo_pins)
icg->setPort(port, Const(0, 1));
// Fix CE polarity if needed
if (!clk.pol_ce) {
SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
SigBit ce_fixed_pol = module->NotGate(NEWER_ID, clk.ce_bit);
icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
}
}

4
passes/techmap/constmap.cc
View file

@ -32,8 +32,8 @@ static RTLIL::SigChunk value;
void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
value = module->addWire(NEWER_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
sig = value;

8
passes/techmap/demuxmap.cc
View file

@ -57,13 +57,13 @@ struct DemuxmapPass : public Pass {
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), out[i]);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
} else {
Wire *eq = module->addWire(NEW_ID);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
Wire *eq = module->addWire(NEWER_ID);
RTLIL::Cell *eq_cell = module->addEq(NEWER_ID, sel, Const(i, GetSize(sel)), eq);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
RTLIL::Cell *mux = module->addMux(NEW_ID,
RTLIL::Cell *mux = module->addMux(NEWER_ID,
Const(State::S0, width),
data,
eq,

42
passes/techmap/dfflegalize.cc
View file

@ -280,7 +280,7 @@ struct DffLegalizePass : public Pass {
void emulate_split_init_arst(FfData &ff) {
ff.remove();
FfData ff_dff(ff.module, &initvals, NEW_ID);
FfData ff_dff(ff.module, &initvals, NEWER_ID);
ff_dff.width = ff.width;
ff_dff.has_aload = ff.has_aload;
ff_dff.sig_aload = ff.sig_aload;
@ -293,11 +293,11 @@ struct DffLegalizePass : public Pass {
ff_dff.has_ce = ff.has_ce;
ff_dff.sig_ce = ff.sig_ce;
ff_dff.pol_ce = ff.pol_ce;
ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_dff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_dff.val_init = ff.val_init;
ff_dff.is_fine = ff.is_fine;
FfData ff_adff(ff.module, &initvals, NEW_ID);
FfData ff_adff(ff.module, &initvals, NEWER_ID);
ff_adff.width = ff.width;
ff_adff.has_aload = ff.has_aload;
ff_adff.sig_aload = ff.sig_aload;
@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass {
ff_adff.has_ce = ff.has_ce;
ff_adff.sig_ce = ff.sig_ce;
ff_adff.pol_ce = ff.pol_ce;
ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_adff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_adff.val_init = Const(State::Sx, ff.width);
ff_adff.has_arst = true;
ff_adff.sig_arst = ff.sig_arst;
@ -318,9 +318,9 @@ struct DffLegalizePass : public Pass {
ff_adff.val_arst = ff.val_arst;
ff_adff.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = 1;
ff_sel.sig_q = ff.module->addWire(NEW_ID);
ff_sel.sig_q = ff.module->addWire(NEWER_ID);
ff_sel.has_arst = true;
ff_sel.sig_arst = ff.sig_arst;
ff_sel.pol_arst = ff.pol_arst;
@ -329,9 +329,9 @@ struct DffLegalizePass : public Pass {
ff_sel.is_fine = ff.is_fine;
if (ff.is_fine)
ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_dff);
legalize_ff(ff_adff);
@ -386,7 +386,7 @@ struct DffLegalizePass : public Pass {
log_assert(ff.width == 1);
ff.remove();
FfData ff_clr(ff.module, &initvals, NEW_ID);
FfData ff_clr(ff.module, &initvals, NEWER_ID);
ff_clr.width = ff.width;
ff_clr.has_aload = ff.has_aload;
ff_clr.sig_aload = ff.sig_aload;
@ -403,11 +403,11 @@ struct DffLegalizePass : public Pass {
ff_clr.sig_arst = ff.sig_clr;
ff_clr.pol_arst = ff.pol_clr;
ff_clr.val_arst = Const(State::S0, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_clr.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width);
ff_clr.is_fine = ff.is_fine;
FfData ff_set(ff.module, &initvals, NEW_ID);
FfData ff_set(ff.module, &initvals, NEWER_ID);
ff_set.width = ff.width;
ff_set.has_aload = ff.has_aload;
ff_set.sig_aload = ff.sig_aload;
@ -424,25 +424,25 @@ struct DffLegalizePass : public Pass {
ff_set.sig_arst = ff.sig_set;
ff_set.pol_arst = ff.pol_set;
ff_set.val_arst = Const(State::S1, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_set.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width);
ff_set.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = ff.width;
ff_sel.has_sr = true;
ff_sel.pol_clr = ff.pol_clr;
ff_sel.pol_set = ff.pol_set;
ff_sel.sig_clr = ff.sig_clr;
ff_sel.sig_set = ff.sig_set;
ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_sel.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_sel.val_init = Const(initsel, ff.width);
ff_sel.is_fine = ff.is_fine;
if (!ff.is_fine)
ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_clr);
legalize_ff(ff_set);
@ -841,11 +841,11 @@ struct DffLegalizePass : public Pass {
ff.sig_ad = State::S0;
ff.val_arst = State::S1;
ff.remove_init();
Wire *new_q = ff.module->addWire(NEW_ID);
Wire *new_q = ff.module->addWire(NEWER_ID);
if (ff.is_fine)
ff.module->addNotGate(NEW_ID, new_q, ff.sig_q);
ff.module->addNotGate(NEWER_ID, new_q, ff.sig_q);
else
ff.module->addNot(NEW_ID, new_q, ff.sig_q);
ff.module->addNot(NEWER_ID, new_q, ff.sig_q);
ff.sig_q = new_q;
if (ff.val_init == State::S0)
ff.val_init = State::S1;
@ -938,9 +938,9 @@ struct DffLegalizePass : public Pass {
} else if (sig == State::S1) {
sig = State::S0;
} else if (ff.is_fine) {
sig = ff.module->NotGate(NEW_ID, sig);
sig = ff.module->NotGate(NEWER_ID, sig);
} else {
sig = ff.module->Not(NEW_ID, sig);
sig = ff.module->Not(NEWER_ID, sig);
}
pol = !pol;
}

10
passes/techmap/dfflibmap.cc
View file

@ -529,25 +529,25 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, GetSize(old_sig));
sig = module->addWire(NEWER_ID, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID::Y), sig);
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
it->setPort(ID::Y, module->addWire(NEWER_ID, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
module->addNotGate(NEWER_ID, sig, old_sig);
}
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);
sig = module->NotGate(NEWER_ID, sig);
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
} else
if (port.second == 0) {
sig = module->addWire(NEW_ID);
sig = module->addWire(NEWER_ID);
} else
log_abort();
new_cell->setPort("\\" + port.first, sig);

8
passes/techmap/extract_counter.cc
View file

@ -639,8 +639,8 @@ void counter_worker(
//If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset)
if(extract.rst_inverted)
{
auto realreset = cell->module->addWire(NEW_ID);
cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset));
auto realreset = cell->module->addWire(NEWER_ID);
cell->module->addNot(NEWER_ID, extract.rst, RTLIL::SigSpec(realreset));
cell->setPort(ID(RST), realreset);
}
else
@ -665,8 +665,8 @@ void counter_worker(
cell->setParam(ID(HAS_CE), RTLIL::Const(1));
if(extract.ce_inverted)
{
auto realce = cell->module->addWire(NEW_ID);
cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce));
auto realce = cell->module->addWire(NEWER_ID);
cell->module->addNot(NEWER_ID, extract.ce, RTLIL::SigSpec(realce));
cell->setPort(ID(CE), realce);
}
else

36
passes/techmap/extract_fa.cc
View file

@ -282,7 +282,7 @@ struct ExtractFaWorker
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
cell->setPort(ID::Y, module->addWire(NEWER_ID));
module->connect(bit, new_driver);
}
}
@ -394,17 +394,17 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEWER_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEWER_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEWER_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEWER_ID);
Y = module->addWire(NEWER_ID);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
@ -414,18 +414,18 @@ struct ExtractFaWorker
bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
if (func3.at(key).count(xor3_func)) {
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEWER_ID, Y) : Y;
for (auto bit : func3.at(key).at(xor3_func))
assign_new_driver(bit, YY);
}
if (func3.at(key).count(xnor3_func)) {
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEWER_ID, Y);
for (auto bit : func3.at(key).at(xnor3_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEWER_ID, X) : X;
for (auto bit : func3.at(key).at(func))
assign_new_driver(bit, XX);
@ -501,35 +501,35 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEWER_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEWER_ID, B) : B);
cell->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEWER_ID);
Y = module->addWire(NEWER_ID);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
}
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEWER_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}
if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEWER_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEWER_ID, X) : X;
for (auto bit : func2.at(key).at(func))
assign_new_driver(bit, XX);

6
passes/techmap/extract_reduce.cc
View file

@ -270,11 +270,11 @@ struct ExtractReducePass : public Pass
}
if (head_cell->type == ID($_AND_)) {
module->addReduceAnd(NEW_ID, input, output);
module->addReduceAnd(NEWER_ID, input, output);
} else if (head_cell->type == ID($_OR_)) {
module->addReduceOr(NEW_ID, input, output);
module->addReduceOr(NEWER_ID, input, output);
} else if (head_cell->type == ID($_XOR_)) {
module->addReduceXor(NEW_ID, input, output);
module->addReduceXor(NEWER_ID, input, output);
} else {
log_assert(false);
}

4
passes/techmap/extractinv.cc
View file

@ -105,10 +105,10 @@ struct ExtractinvPass : public Pass {
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
continue;
Wire *iwire = module->addWire(NEW_ID, sig.size());
Wire *iwire = module->addWire(NEWER_ID, sig.size());
for (int i = 0; i < sig.size(); i++)
if (invmask[i] == State::S1) {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
RTLIL::Cell *icell = module->addCell(NEWER_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i);

4
passes/techmap/flowmap.cc
View file

@ -1411,7 +1411,7 @@ struct FlowmapWorker
if ((int)input_nodes.size() < minlut)
lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
RTLIL::Cell *lut = module->addLut(NEWER_ID, lut_a, lut_y, lut_table);
mapped_nodes.insert(node);
for (auto gate_node : lut_gates[node])
{
@ -1432,7 +1432,7 @@ struct FlowmapWorker
{
auto origin = node_origins[node];
RTLIL::SigSpec driver = origin.cell->getPort(origin.port);
driver[origin.offset] = module->addWire(NEW_ID);
driver[origin.offset] = module->addWire(NEWER_ID);
origin.cell->setPort(origin.port, driver);
}
}

8
passes/techmap/hilomap.cc
View file

@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &bit : sig) {
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
last_hi = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(hicell_celltype));
cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
last_lo = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(locell_celltype));
cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;

2
passes/techmap/insbuf.cc
View file

@ -94,7 +94,7 @@ struct InsbufPass : public Pass {
sigmap.add(outbit);
}
Cell *cell = module->addCell(NEW_ID, celltype);
Cell *cell = module->addCell(NEWER_ID, celltype);
cell->setPort(in_portname, rhs);
cell->setPort(out_portname, lhs);

4
passes/techmap/iopadmap.cc
View file

@ -331,7 +331,7 @@ struct IopadmapPass : public Pass {
RTLIL::escape_id(tinoutpad_celltype));
if (tinoutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
en_sig = module->NotGate(NEWER_ID, en_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
@ -355,7 +355,7 @@ struct IopadmapPass : public Pass {
RTLIL::escape_id(toutpad_celltype));
if (toutpad_neg_oe)
en_sig = module->NotGate(NEW_ID, en_sig);
en_sig = module->NotGate(NEWER_ID, en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);

12
passes/techmap/lut2mux.cc
View file

@ -32,22 +32,22 @@ int lut2mux(Cell *cell)
if (GetSize(sig_a) == 1)
{
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
cell->module->addMuxGate(NEWER_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
}
else
{
SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
SigSpec sig_y1 = cell->module->addWire(NEW_ID);
SigSpec sig_y2 = cell->module->addWire(NEW_ID);
SigSpec sig_y1 = cell->module->addWire(NEWER_ID);
SigSpec sig_y2 = cell->module->addWire(NEWER_ID);
Const lut1 = lut.extract(0, GetSize(lut)/2);
Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y1, lut1));
count += lut2mux(cell->module->addLut(NEWER_ID, sig_a_lo, sig_y2, lut2));
cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
cell->module->addMuxGate(NEWER_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
}
cell->module->remove(cell);

40
passes/techmap/maccmap.cc
View file

@ -52,7 +52,7 @@ struct MaccmapWorker
a.extend_u0(width, is_signed);
if (do_subtract) {
a = module->Not(NEW_ID, a);
a = module->Not(NEWER_ID, a);
add(State::S1, 0);
}
@ -73,13 +73,13 @@ struct MaccmapWorker
for (int i = 0; i < GetSize(b); i++)
if (is_signed && i+1 == GetSize(b))
{
a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {module->Not(NEWER_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract);
}
else
{
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
add(module->And(NEWER_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {a.extract(0, width-1), State::S0};
}
}
@ -108,10 +108,10 @@ struct MaccmapWorker
in3 = in3.extract(start_index, stop_index-start_index);
int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Wire *w1 = module->addWire(NEWER_ID, width);
RTLIL::Wire *w2 = module->addWire(NEWER_ID, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($fa));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
@ -237,14 +237,14 @@ struct MaccmapWorker
}
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
RTLIL::Cell *c = module->addCell(NEWER_ID, ID($alu));
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
c->setPort(ID::CI, State::S0);
c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID::X, module->addWire(NEW_ID, width));
c->setPort(ID::CO, module->addWire(NEW_ID, width));
c->setPort(ID::Y, module->addWire(NEWER_ID, width));
c->setPort(ID::X, module->addWire(NEWER_ID, width));
c->setPort(ID::CO, module->addWire(NEWER_ID, width));
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
@ -296,16 +296,16 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &term : macc.terms) {
summand_t this_summand;
if (GetSize(term.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEWER_ID, width);
module->addMul(NEWER_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
} else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) {
// Mimic old 'bit_terms' treatment in case it's relevant for performance,
// i.e. defer single-bit summands to be the last ones
bit_terms.append(term.in_a);
continue;
} else if (GetSize(term.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEWER_ID, width);
module->addPos(NEWER_ID, term.in_a, this_summand.first, term.is_signed);
} else {
this_summand.first = term.in_a;
}
@ -325,14 +325,14 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (int i = 0; i < GetSize(summands); i += 2) {
if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEWER_ID, width);
this_summand.second = summands[i].second && summands[i+1].second;
if (summands[i].second == summands[i+1].second)
module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addAdd(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first);
else if (summands[i].second)
module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first);
module->addSub(NEWER_ID, summands[i+1].first, summands[i].first, this_summand.first);
else if (summands[i+1].second)
module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addSub(NEWER_ID, summands[i].first, summands[i+1].first, this_summand.first);
else
log_abort();
new_summands.push_back(this_summand);
@ -343,7 +343,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
if (summands.front().second)
module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y));
module->addNeg(NEWER_ID, summands.front().first, cell->getPort(ID::Y));
else
module->connect(cell->getPort(ID::Y), summands.front().first);
}

16
passes/techmap/muxcover.cc
View file

@ -185,7 +185,7 @@ struct MuxcoverWorker
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
if (decode_mux_cache.count(key) == 0) {
auto &entry = decode_mux_cache[key];
std::get<0>(entry) = module->addWire(NEW_ID);
std::get<0>(entry) = module->addWire(NEWER_ID);
std::get<2>(entry) = false;
decode_mux_reverse_cache[std::get<0>(entry)] = key;
}
@ -215,11 +215,11 @@ struct MuxcoverWorker
implement_decode_mux(std::get<1>(key));
if (std::get<0>(key) == State::Sx) {
module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit);
module->addBufGate(NEWER_ID, std::get<1>(key), ctrl_bit);
} else if (std::get<1>(key) == State::Sx) {
module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit);
module->addBufGate(NEWER_ID, std::get<0>(key), ctrl_bit);
} else {
module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
module->addMuxGate(NEWER_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
decode_mux_counter++;
}
std::get<2>(entry) = true;
@ -513,7 +513,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::S, mux.selects[0]);
@ -523,7 +523,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX4_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
@ -536,7 +536,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX8_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
@ -554,7 +554,7 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
Cell *cell = module->addCell(NEWER_ID, ID($_MUX16_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);

10
passes/techmap/pmuxtree.cc
View file

@ -32,9 +32,9 @@ static SigSpec or_generator(Module *module, const SigSpec &sig)
case 1:
return sig;
case 2:
return module->Or(NEW_ID, sig[0], sig[1]);
return module->Or(NEWER_ID, sig[0], sig[1]);
default:
return module->ReduceOr(NEW_ID, sig);
return module->ReduceOr(NEWER_ID, sig);
}
}
@ -62,7 +62,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data,
left_or = or_generator(module, left_or);
sig_or.append(left_or);
return module->Mux(NEW_ID, right_result, left_result, left_or);
return module->Mux(NEWER_ID, right_result, left_result, left_or);
}
struct PmuxtreePass : public Pass {
@ -97,8 +97,8 @@ struct PmuxtreePass : public Pass {
if (!cell->getPort(ID::A).is_fully_undef()) {
sig_data.append(cell->getPort(ID::A));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or));
SigSpec sig_sel_or = module->ReduceOr(NEWER_ID, sig_sel);
sig_sel.append(module->Not(NEWER_ID, sig_sel_or));
}
SigSpec result, result_or;

4
passes/techmap/shregmap.cc
View file

@ -75,7 +75,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech
auto D = cell->getPort(ID::D);
auto C = cell->getPort(ID::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
auto newcell = cell->module->addCell(NEWER_ID, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
newcell->setPort(ID::CLK, C);
newcell->setPort(ID(IN), D);
@ -142,7 +142,7 @@ struct ShregmapWorker
// so that it can be identified as another chain
// (omitting this common flop)
// Link: https://github.com/YosysHQ/yosys/pull/1085
Wire *wire = module->addWire(NEW_ID);
Wire *wire = module->addWire(NEWER_ID);
module->connect(wire, d_bit);
sigmap.add(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));

48
passes/techmap/simplemap.cc
View file

@ -35,7 +35,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
@ -80,7 +80,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -122,7 +122,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig_a.size() / 2);
for (int i = 0; i < sig_a.size(); i += 2)
{
@ -131,7 +131,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
@ -143,8 +143,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID);
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
@ -163,7 +163,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
{
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig.size() / 2);
for (int i = 0; i < sig.size(); i += 2)
{
@ -172,7 +172,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_OR_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
@ -201,7 +201,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
@ -230,7 +230,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
@ -245,20 +245,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
RTLIL::SigSpec xor_out = module->addWire(NEWER_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEWER_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEWER_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEWER_ID, xor_out, reduce_out);
reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
RTLIL::Cell *not_cell = module->addLogicNot(NEWER_ID, reduce_out, sig_y);
not_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_lognot(module, not_cell);
module->remove(not_cell);
@ -272,7 +272,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -289,7 +289,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -305,7 +305,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_TBUF_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
@ -320,10 +320,10 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
int width = GetSize(cell->getPort(ID::Y));
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
@ -344,9 +344,9 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
SigSpec new_lut_data = module->addWire(NEWER_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
@ -383,10 +383,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
products.append(GetSize(in) > 0 ? module->Eq(NEWER_ID, in, pat) : State::S1);
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEWER_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)

4
passes/techmap/techmap.cc
View file

@ -205,7 +205,7 @@ struct TechmapWorker
RTLIL::Wire *w = module->wire(w_name);
if (w != nullptr) {
temp_renamed_wires[w] = w->name;
module->rename(w, NEW_ID);
module->rename(w, NEWER_ID);
w = nullptr;
}
if (w == nullptr) {
@ -792,7 +792,7 @@ struct TechmapWorker
continue;
IdString port_name = wire->name;
tpl->rename(wire, NEW_ID);
tpl->rename(wire, NEWER_ID);
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
wire->port_input = false;

12
passes/techmap/tribuf.cc
View file

@ -93,7 +93,7 @@ struct TribufWorker {
}
if (is_all_z(cell->getPort(ID::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->setPort(en_port, module->Not(NEWER_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
cell->type = tri_type;
@ -138,12 +138,12 @@ struct TribufWorker {
auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E);
auto other_s = module->ReduceOr(NEW_ID, others_s);
auto other_s = module->ReduceOr(NEWER_ID, others_s);
auto conflict = module->And(NEW_ID, cell_s, other_s);
auto conflict = module->And(NEWER_ID, cell_s, other_s);
std::string name = stringf("$tribuf_conflict$%s", log_id(cell->name));
auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true));
auto assert_cell = module->addAssert(name, module->Not(NEWER_ID, conflict), SigSpec(true));
assert_cell->set_src_attribute(cell->get_src_attribute());
assert_cell->set_bool_attribute(ID::keep);
@ -162,12 +162,12 @@ struct TribufWorker {
module->remove(cell);
}
SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b;
SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEWER_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b;
if (no_tribuf)
module->connect(it.first, muxout);
else {
module->addTribuf(NEW_ID, muxout, module->ReduceOr(NEW_ID, pmux_s), it.first);
module->addTribuf(NEWER_ID, muxout, module->ReduceOr(NEWER_ID, pmux_s), it.first);
module->design->scratchpad_set_bool("tribuf.added_something", true);
}
}