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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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16
passes/proc/proc_dff.cc
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@ -66,16 +66,16 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
{
const auto& [sync_value, rule] = *it;
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEWER_ID, rule->signal);
// If pos_trig is true, we have priority at this point in the tree so
// set a bit if sync_value has a set bit. Otherwise, defer to the rest
// of the priority tree
sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
sig_sr_set = mod->Mux(NEWER_ID, sig_sr_set, sync_value, pos_trig);
// Same deal with clear bit
const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
const auto sync_value_inv = mod->Not(NEWER_ID, sync_value);
sig_sr_clr = mod->Mux(NEWER_ID, sig_sr_clr, sync_value_inv, pos_trig);
}
std::stringstream sstr;
@ -217,12 +217,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
// (with appropriate negation)
RTLIL::SigSpec triggers;
for (const auto &[_, it] : async_rules)
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEWER_ID, it->signal));
// Put this into the dummy sync rule so it can be treated the same
// as ones coming from the module
single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
single_async_rule.signal = mod->ReduceOr(NEWER_ID, triggers);
single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
// Replace existing rules with this new rule
@ -239,9 +239,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (async_rules.size() == 1 && async_rules.front().first == sig) {
const auto& [_, rule] = async_rules.front();
if (rule->type == RTLIL::SyncType::ST1)
insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
insig = mod->Mux(NEWER_ID, insig, sig, rule->signal);
else
insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
insig = mod->Mux(NEWER_ID, sig, insig, rule->signal);
async_rules.clear();
}