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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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6
passes/pmgen/README.md
View file

@ -367,9 +367,9 @@ test-case generation. For example:
...
generate 10 0
SigSpec Y = port(ff, \D);
SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
module->addMul(NEW_ID, A, B, Y, rng(2));
SigSpec A = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEWER_ID, GetSize(Y) - rng(GetSize(Y)/2));
module->addMul(NEWER_ID, A, B, Y, rng(2));
endmatch
The expression `rng(n)` returns a non-negative integer less than `n`.

4
passes/pmgen/generate.h
View file

@ -78,7 +78,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
while (modcnt < maxmodcnt)
{
int submodcnt = 0, itercnt = 0, cellcnt = 0;
Module *mod = design->addModule(NEW_ID);
Module *mod = design->addModule(NEWER_ID);
while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
{
@ -130,7 +130,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);
for (auto port : mod->ports) {
Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port)));
Wire *w = m->addWire(NEWER_ID, GetSize(mod->wire(port)));
c->setPort(port, w);
}
}

14
passes/pmgen/test_pmgen.cc
View file

@ -58,11 +58,11 @@ void reduce_chain(test_pmgen_pm &pm)
Cell *c;
if (last_cell->type == ID($_AND_))
c = pm.module->addReduceAnd(NEW_ID, A, Y);
c = pm.module->addReduceAnd(NEWER_ID, A, Y);
else if (last_cell->type == ID($_OR_))
c = pm.module->addReduceOr(NEW_ID, A, Y);
c = pm.module->addReduceOr(NEWER_ID, A, Y);
else if (last_cell->type == ID($_XOR_))
c = pm.module->addReduceXor(NEW_ID, A, Y);
c = pm.module->addReduceXor(NEWER_ID, A, Y);
else
log_abort();
@ -87,11 +87,11 @@ void reduce_tree(test_pmgen_pm &pm)
Cell *c;
if (st.first->type == ID($_AND_))
c = pm.module->addReduceAnd(NEW_ID, A, Y);
c = pm.module->addReduceAnd(NEWER_ID, A, Y);
else if (st.first->type == ID($_OR_))
c = pm.module->addReduceOr(NEW_ID, A, Y);
c = pm.module->addReduceOr(NEWER_ID, A, Y);
else if (st.first->type == ID($_XOR_))
c = pm.module->addReduceXor(NEW_ID, A, Y);
c = pm.module->addReduceXor(NEWER_ID, A, Y);
else
log_abort();
@ -112,7 +112,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
Cell *c = pm.module->addMux(NEWER_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
}

42
passes/pmgen/test_pmgen.pmg
View file

@ -14,19 +14,19 @@ match first
select first->type.in($_AND_, $_OR_, $_XOR_)
filter !non_first_cells.count(first)
generate
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec Y = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEWER_ID);
SigSpec B = module->addWire(NEWER_ID);
SigSpec Y = module->addWire(NEWER_ID);
switch (rng(3))
{
case 0:
module->addAndGate(NEW_ID, A, B, Y);
module->addAndGate(NEWER_ID, A, B, Y);
break;
case 1:
module->addOrGate(NEW_ID, A, B, Y);
module->addOrGate(NEWER_ID, A, B, Y);
break;
case 2:
module->addXorGate(NEW_ID, A, B, Y);
module->addXorGate(NEWER_ID, A, B, Y);
break;
}
endmatch
@ -82,10 +82,10 @@ match next
index <IdString> next->type === chain.back().first->type
index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
generate 10
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEWER_ID);
SigSpec B = module->addWire(NEWER_ID);
SigSpec Y = port(chain.back().first, chain.back().second);
Cell *c = module->addAndGate(NEW_ID, A, B, Y);
Cell *c = module->addAndGate(NEWER_ID, A, B, Y);
c->type = chain.back().first->type;
endmatch
@ -121,10 +121,10 @@ match eq
set eq_inB port(eq, \B)
set eq_ne_signed param(eq, \A_SIGNED).as_bool()
generate 100 10
SigSpec A = module->addWire(NEW_ID, rng(7)+1);
SigSpec B = module->addWire(NEW_ID, rng(7)+1);
SigSpec Y = module->addWire(NEW_ID);
module->addEq(NEW_ID, A, B, Y, rng(2));
SigSpec A = module->addWire(NEWER_ID, rng(7)+1);
SigSpec B = module->addWire(NEWER_ID, rng(7)+1);
SigSpec Y = module->addWire(NEWER_ID);
module->addEq(NEWER_ID, A, B, Y, rng(2));
endmatch
match pmux
@ -137,16 +137,16 @@ generate 100 10
int numsel = rng(4) + 1;
int idx = rng(numsel);
SigSpec A = module->addWire(NEW_ID, width);
SigSpec Y = module->addWire(NEW_ID, width);
SigSpec A = module->addWire(NEWER_ID, width);
SigSpec Y = module->addWire(NEWER_ID, width);
SigSpec B, S;
for (int i = 0; i < numsel; i++) {
B.append(module->addWire(NEW_ID, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
B.append(module->addWire(NEWER_ID, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEWER_ID));
}
module->addPmux(NEW_ID, A, B, S, Y);
module->addPmux(NEWER_ID, A, B, S, Y);
endmatch
match ne
@ -169,11 +169,11 @@ generate 100 10
if (GetSize(Y))
Y = Y[rng(GetSize(Y))];
else
Y = module->addWire(NEW_ID);
Y = module->addWire(NEWER_ID);
} else {
Y = module->addWire(NEW_ID);
Y = module->addWire(NEWER_ID);
}
module->addNe(NEW_ID, A, B, Y, rng(2));
module->addNe(NEWER_ID, A, B, Y, rng(2));
endmatch
match pmux2