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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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68
passes/opt/opt_expr.cc
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@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
if (grouped_bits[i].empty())
continue;
RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_y = module->addWire(NEWER_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_a, new_b;
RTLIL::SigSig new_conn;
@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[i] == State::S0 || new_a[i] == State::S1) {
undef_a.append(new_a[i]);
if (cell->type == ID($xor))
undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]);
undef_b.append(new_a[i] == State::S1 ? module->Not(NEWER_ID, new_b[i]).as_bit() : new_b[i]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit());
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEWER_ID, new_b[i]).as_bit());
else log_abort();
undef_y.append(new_y[i]);
}
@ -273,7 +273,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -612,9 +612,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
sig_y = (sig_b == State::S1 ? module->Not(NEWER_ID, sig_a).as_bit() : sig_a);
else if (cell->type == ID($_XOR_))
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
sig_y = (sig_b == State::S1 ? module->NotGate(NEWER_ID, sig_a) : sig_a);
else log_abort();
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
goto next_cell;
@ -623,12 +623,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEWER_ID, sig_a).as_bit());
int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEWER_ID, sig_a));
else log_abort();
replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
goto next_cell;
@ -698,7 +698,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = b_group_1;
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->And(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(y_group_x));
}
@ -707,16 +707,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1));
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Or(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(y_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!y_group_0.empty()) y_new_0 = b_group_0;
if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1);
if (!y_group_1.empty()) y_new_1 = module->Not(NEWER_ID, b_group_1);
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Xor(NEWER_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(y_group_x));
}
@ -779,11 +779,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1);
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, module->Not(NEWER_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, s_group_1);
} else {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1));
if (!y_group_0.empty()) y_new_0 = module->And(NEWER_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEWER_ID, b_group_1, module->Not(NEWER_ID, s_group_1));
}
module->connect(y_group_0, y_new_0);
@ -996,12 +996,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEWER_ID, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEWER_ID, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1428,7 +1428,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(ID::A);
a.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
module->connect(cell->getPort(ID::X), module->Not(NEWER_ID, a));
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
} else {
/* add */
@ -1733,10 +1733,10 @@ skip_identity:
cell->parameters[ID::A_SIGNED] = 0;
cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
SigSpec y_wire = module->addWire(NEW_ID, y_size);
SigSpec y_wire = module->addWire(NEWER_ID, y_size);
cell->setPort(ID::Y, y_wire);
module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
module->addShl(NEWER_ID, Const(State::S1, 1), y_wire, sig_y);
}
did_something = true;
goto next_cell;
@ -1889,13 +1889,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEWER_ID, sig_y.size());
cell->setPort(ID::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEWER_ID, a_sign, rem_nonzero);
module->addAdd(NEWER_ID, flooring, should_add, sig_y);
}
cell->check();
@ -1917,11 +1917,11 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = module->ReduceOr(NEWER_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEWER_ID, a_sign, rem_nonzero);
truncating.append(extend_bit);
module->addPos(NEW_ID, truncating, sig_y, true);
module->addPos(NEWER_ID, truncating, sig_y, true);
}
else
{
@ -2004,7 +2004,7 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
RTLIL::Cell *c = module->addCell(NEWER_ID, cell->type);
c->setPort(ID::A, sig_a.extract(prev, sz));
c->setPort(ID::B, sig_b.extract(prev, sz));
c->setPort(ID::BI, sig_bi);
@ -2014,7 +2014,7 @@ skip_identity:
RTLIL::SigSpec new_co = sig_co.extract(prev, sz);
if (p.second != State::Sx) {
module->connect(new_co[sz-1], p.second);
RTLIL::Wire *dummy = module->addWire(NEW_ID);
RTLIL::Wire *dummy = module->addWire(NEWER_ID);
new_co[sz-1] = dummy;
}
c->setPort(ID::CO, new_co);
@ -2181,14 +2181,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addReduceOr(NEWER_ID, var_high_sig, cell->getPort(ID::Y));
remove = true;
}
}
@ -2230,7 +2230,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
module->addLogicNot(NEWER_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
remove = true;
}
}