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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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2
passes/hierarchy/flatten.cc
View file

@ -273,7 +273,7 @@ struct FlattenWorker
if (create_scopeinfo && cell_name.isPublic())
{
// The $scopeinfo's name will be changed below after removing the flattened cell
scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
scopeinfo = module->addCell(NEWER_ID, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
for (auto const &attr : cell->attributes)

12
passes/hierarchy/hierarchy.cc
View file

@ -1370,7 +1370,7 @@ struct HierarchyPass : public Pass {
continue;
}
Wire *t = module->addWire(NEW_ID, GetSize(c));
Wire *t = module->addWire(NEWER_ID, GetSize(c));
new_sig.append(t);
update_port = true;
@ -1400,18 +1400,18 @@ struct HierarchyPass : public Pass {
if (GetSize(w) == 1) {
if (wand)
module->addReduceAnd(NEW_ID, sigs, w);
module->addReduceAnd(NEWER_ID, sigs, w);
else
module->addReduceOr(NEW_ID, sigs, w);
module->addReduceOr(NEWER_ID, sigs, w);
continue;
}
SigSpec s = sigs.extract(0, GetSize(w));
for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
if (wand)
s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
s = module->And(NEWER_ID, s, sigs.extract(i, GetSize(w)));
else
s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
s = module->Or(NEWER_ID, s, sigs.extract(i, GetSize(w)));
}
module->connect(w, s);
}
@ -1473,7 +1473,7 @@ struct HierarchyPass : public Pass {
if (w->port_input && !w->port_output)
sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
sig.append(module->addWire(NEWER_ID, n));
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)

4
passes/hierarchy/submod.cc
View file

@ -232,10 +232,10 @@ struct SubmodWorker
auto &b = old_sig[i];
// Prevents "ERROR: Mismatch in directionality ..." when flattening
if (!b.wire)
b = module->addWire(NEW_ID);
b = module->addWire(NEWER_ID);
// Prevents "Warning: multiple conflicting drivers ..."
else if (!it.second.is_int_driven[i])
b = module->addWire(NEW_ID);
b = module->addWire(NEWER_ID);
}
new_cell->setPort(new_wire->name, old_sig);
}