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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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14
passes/equiv/equiv_add.cc
View file

@ -84,10 +84,10 @@ struct EquivAddPass : public Pass {
if (gold_cell->input(port) && gate_cell->input(port))
{
SigSpec combined_sig = module->addWire(NEW_ID, width);
SigSpec combined_sig = module->addWire(NEWER_ID, width);
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
module->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
gold_sig[i] = gate_sig[i] = combined_sig[i];
}
@ -98,12 +98,12 @@ struct EquivAddPass : public Pass {
if (gold_cell->output(port) && gate_cell->output(port))
{
SigSpec new_gold_wire = module->addWire(NEW_ID, width);
SigSpec new_gate_wire = module->addWire(NEW_ID, width);
SigSpec new_gold_wire = module->addWire(NEWER_ID, width);
SigSpec new_gate_wire = module->addWire(NEWER_ID, width);
SigSig gg_conn;
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
module->addEquiv(NEWER_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
gg_conn.first.append(gate_sig[i]);
gg_conn.second.append(gold_sig[i]);
gold_sig[i] = new_gold_wire[i];
@ -141,7 +141,7 @@ struct EquivAddPass : public Pass {
}
log_assert(GetSize(gold_signal) == GetSize(gate_signal));
SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
SigSpec equiv_signal = module->addWire(NEWER_ID, GetSize(gold_signal));
SigMap sigmap(module);
sigmap.apply(gold_signal);
@ -151,7 +151,7 @@ struct EquivAddPass : public Pass {
pool<Cell*> added_equiv_cells;
for (int i = 0; i < GetSize(gold_signal); i++) {
Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
Cell *equiv_cell = module->addEquiv(NEWER_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
equiv_cell->set_bool_attribute(ID::keep);
to_equiv_bits[gold_signal[i]] = equiv_signal[i];
to_equiv_bits[gate_signal[i]] = equiv_signal[i];

24
passes/equiv/equiv_make.cc
View file

@ -136,8 +136,8 @@ struct EquivMakeWorker
void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig)
{
auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig);
equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1);
auto eq_wire = equiv_mod->Eqx(NEWER_ID, gold_sig, gate_sig);
equiv_mod->addAssert(NEWER_ID_SUFFIX("assert"), eq_wire, State::S1);
}
void find_same_wires()
@ -205,11 +205,11 @@ struct EquivMakeWorker
for (auto &bit : enc_result)
if (bit != State::S1) bit = State::S0;
SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
SigSpec dec_eq = equiv_mod->addWire(NEWER_ID);
SigSpec enc_eq = equiv_mod->addWire(NEWER_ID);
equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
equiv_mod->addEq(NEWER_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEWER_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
dec_s.append(dec_eq);
enc_s.append(enc_eq);
@ -217,8 +217,8 @@ struct EquivMakeWorker
enc_b.append(enc_result);
}
equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire);
equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire);
equiv_mod->addPmux(NEWER_ID, dec_a, dec_b, dec_s, dec_wire);
equiv_mod->addPmux(NEWER_ID, enc_a, enc_b, enc_s, enc_wire);
rd_signal_map.add(assign_map(gate_wire), enc_wire);
gate_wire = dec_wire;
@ -254,7 +254,7 @@ struct EquivMakeWorker
else
{
for (int i = 0; i < wire->width; i++)
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
}
rd_signal_map.add(assign_map(gold_wire), wire);
@ -291,7 +291,7 @@ struct EquivMakeWorker
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
continue;
}
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
equiv_mod->addEquiv(NEWER_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
rdmap_gold.append(SigBit(gold_wire, i));
rdmap_gate.append(SigBit(gate_wire, i));
rdmap_equiv.append(SigBit(wire, i));
@ -365,8 +365,8 @@ struct EquivMakeWorker
{
for (int i = 0; i < GetSize(gold_sig); i++)
if (gold_sig[i] != gate_sig[i]) {
Wire *w = equiv_mod->addWire(NEW_ID);
equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
Wire *w = equiv_mod->addWire(NEWER_ID);
equiv_mod->addEquiv(NEWER_ID, gold_sig[i], gate_sig[i], w);
gold_sig[i] = w;
}
}

12
passes/equiv/equiv_miter.cc
View file

@ -219,9 +219,9 @@ struct EquivMiterWorker
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
miter_module->LogicOr(NEWER_ID, miter_module->Eqx(NEWER_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEWER_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
@ -236,15 +236,15 @@ struct EquivMiterWorker
}
if (mode_assert)
miter_module->addAssert(NEW_ID, cmp, State::S1);
miter_module->addAssert(NEWER_ID, cmp, State::S1);
trigger_signals.append(miter_module->Not(NEW_ID, cmp));
trigger_signals.append(miter_module->Not(NEWER_ID, cmp));
}
if (mode_trigger) {
auto w = miter_module->addWire(ID(trigger));
w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w);
miter_module->addReduceOr(NEWER_ID, trigger_signals, w);
}
miter_module->fixup_ports();

4
passes/equiv/equiv_purge.cc
View file

@ -67,7 +67,7 @@ struct EquivPurgeWorker
log(" Module input: %s\n", log_signal(wire));
wire->port_input = true;
}
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEWER_ID, GetSize(sig));
}
}
@ -81,7 +81,7 @@ struct EquivPurgeWorker
wire->port_input = true;
module->connect(sig, wire);
log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig));
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEWER_ID, GetSize(sig));
}
}

4
passes/equiv/equiv_struct.cc
View file

@ -85,10 +85,10 @@ struct EquivStructWorker
for (int i = 0; i < GetSize(inputs_a); i++) {
SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
SigBit bit_y = module->addWire(NEW_ID);
SigBit bit_y = module->addWire(NEWER_ID);
log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
module->addEquiv(NEWER_ID, bit_a, bit_b, bit_y);
merged_map.add(bit_a, bit_y);
merged_map.add(bit_b, bit_y);
}