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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent 6b9082fa64
commit 73d51b25d6
130 changed files with 1275 additions and 1275 deletions
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16
passes/cmds/abstract.cc
View file

@ -82,7 +82,7 @@ struct Slice {
};
void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) {
auto anyseq = mod->Anyseq(NEW_ID, mux_input.size());
auto anyseq = mod->Anyseq(NEWER_ID, mux_input.size());
if (enable.bit == (enable.pol ? State::S1 : State::S0)) {
mod->connect(mux_output, anyseq);
}
@ -94,7 +94,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
mux_a = anyseq;
mux_b = mux_input;
}
(void)mod->addMux(NEW_ID,
(void)mod->addMux(NEWER_ID,
mux_a,
mux_b,
enable.bit,
@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
}
bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
Wire* abstracted = ff.module->addWire(NEWER_ID, offsets.size());
SigSpec mux_input;
int abstracted_idx = 0;
for (int d_idx = 0; d_idx < ff.width; d_idx++) {
@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
}
bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
Wire* to_abstract = mod->addWire(NEWER_ID, offsets.size());
SigSpec mux_input;
SigSpec mux_output;
const SigSpec& old_port = cell->getPort(port_name);
@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, Id
}
bool abstract_value_mod_port(Module* mod, Wire* wire, std::set<int> offsets, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, wire);
Wire* to_abstract = mod->addWire(NEWER_ID, wire);
to_abstract->port_input = true;
to_abstract->port_id = wire->port_id;
wire->port_input = false;
@ -501,10 +501,10 @@ struct AbstractPass : public Pass {
enable_logic = { enable_wire, enable == Enable::ActiveHigh };
} break;
case Enable::Initstates: {
SigBit in_init_states = mod->Initstate(NEW_ID);
SigBit in_init_states = mod->Initstate(NEWER_ID);
for (int i = 1; i < initstates; i++) {
Wire *in_init_states_q = mod->addWire(NEW_ID);
mod->addFf(NEW_ID, in_init_states, in_init_states_q);
Wire *in_init_states_q = mod->addWire(NEWER_ID);
mod->addFf(NEWER_ID, in_init_states, in_init_states_q);
in_init_states_q->attributes[ID::init] = State::S1;
in_init_states = in_init_states_q;
}

2
passes/cmds/add.cc
View file

@ -41,7 +41,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
RTLIL::Cell *formal_cell = module->addCell(NEWER_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);

2
passes/cmds/bugpoint.cc
View file

@ -306,7 +306,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
RTLIL::Wire *wire = mod->addWire(NEWER_ID, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);

24
passes/cmds/chformal.cc
View file

@ -337,12 +337,12 @@ struct ChformalPass : public Pass {
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort(ID::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
Wire *new_a = module->addWire(NEWER_ID);
Wire *new_en = module->addWire(NEWER_ID);
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
module->addFf(NEWER_ID, orig_a, new_a);
module->addFf(NEWER_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort(ID::EN, new_en);
@ -355,14 +355,14 @@ struct ChformalPass : public Pass {
SigSpec en = State::S1;
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEWER_ID);
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
module->addFf(NEWER_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
cell->setPort(ID::EN, module->LogicAnd(NEWER_ID, en, cell->getPort(ID::EN)));
}
else
if (mode =='p')
@ -370,7 +370,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (cell->type == ID($check)) {
Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
Cell *cover = module->addCell(NEWER_ID_SUFFIX("coverenable"), ID($check));
cover->attributes = cell->attributes;
cover->parameters = cell->parameters;
cover->setParam(ID(FLAVOR), Const("cover"));
@ -381,7 +381,7 @@ struct ChformalPass : public Pass {
cover->setPort(ID::A, cell->getPort(ID::EN));
cover->setPort(ID::EN, State::S1);
} else {
module->addCover(NEW_ID_SUFFIX("coverenable"),
module->addCover(NEWER_ID_SUFFIX("coverenable"),
cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
}
}
@ -414,7 +414,7 @@ struct ChformalPass : public Pass {
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
Cell *plain_cell = module->addCell(NEWER_ID, formal_flavor(cell));
plain_cell->attributes = cell->attributes;
@ -425,9 +425,9 @@ struct ChformalPass : public Pass {
plain_cell->setPort(ID::EN, sig_en);
if (plain_cell->type.in(ID($assert), ID($assume)))
sig_a = module->Not(NEW_ID, sig_a);
sig_a = module->Not(NEWER_ID, sig_a);
SigBit combined_en = module->And(NEW_ID, sig_a, sig_en);
SigBit combined_en = module->And(NEWER_ID, sig_a, sig_en);
module->swap_names(cell, plain_cell);

2
passes/cmds/connect.cc
View file

@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID, sig.size());
for (auto cell : module->cells())
for (auto &port : cell->connections_)

84
passes/cmds/dft_tag.cc
View file

@ -101,7 +101,7 @@ struct DftTagWorker {
log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
auto *set_tag_cell = module->addSetTag(NEWER_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
design_changed = true;
}
@ -123,7 +123,7 @@ struct DftTagWorker {
signal_mapped.sort_and_unify();
if (GetSize(signal_mapped) < GetSize(signal))
log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
SigSpec new_wire = module->addWire(NEWER_ID, GetSize(signal));
for (int i = 0; i < GetSize(new_wire); ++i)
divert_users(signal[i], new_wire[i]);
return new_wire;
@ -318,7 +318,7 @@ struct DftTagWorker {
if (!GetSize(combined))
combined = tag_sig;
else
combined = autoOr(NEW_ID, combined, tag_sig);
combined = autoOr(NEWER_ID, combined, tag_sig);
}
if (!GetSize(combined))
@ -359,7 +359,7 @@ struct DftTagWorker {
// when the outer call for this tag/cell returns
for (auto &conn : cell->connections())
if (cell->output(conn.first))
emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
emit_tag_signal(tag, conn.second, module->addWire(NEWER_ID, GetSize(conn.second)));
return;
}
@ -486,8 +486,8 @@ struct DftTagWorker {
if (cell_tag == tag) {
auto &sig_set = cell->getPort(ID::SET);
auto &sig_clr = cell->getPort(ID::CLR);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, autoNot(NEWER_ID, sig_clr));
tag_sig_a = autoOr(NEWER_ID, tag_sig_a, sig_set);
}
emit_tag_signal(tag, sig_y, tag_sig_a);
@ -529,9 +529,9 @@ struct DftTagWorker {
inv_b ^= true;
if (inv_a)
sig_a = autoNot(NEW_ID, sig_a);
sig_a = autoNot(NEWER_ID, sig_a);
if (inv_b)
sig_b = autoNot(NEW_ID, sig_b);
sig_b = autoNot(NEWER_ID, sig_b);
auto group_sig_a = tag_group_signal(tag, sig_a);
auto group_sig_b = tag_group_signal(tag, sig_b);
@ -541,15 +541,15 @@ struct DftTagWorker {
// Does this input allow propagating (doesn't fix output or same tag group)
sig_a = autoOr(NEW_ID, sig_a, group_sig_a);
sig_b = autoOr(NEW_ID, sig_b, group_sig_b);
sig_a = autoOr(NEWER_ID, sig_a, group_sig_a);
sig_b = autoOr(NEWER_ID, sig_b, group_sig_b);
// Mask input tags by whether the other side allows propagation
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b);
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, sig_b);
tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, sig_a);
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b);
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -566,7 +566,7 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
auto tag_sig = autoOr(NEWER_ID, tag_sig_a, tag_sig_b);
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -585,23 +585,23 @@ struct DftTagWorker {
auto group_sig_b = tag_group_signal(tag, sig_b);
auto group_sig_s = tag_group_signal(tag, sig_s);
auto prop_s = autoOr(NEW_ID,
autoXor(NEW_ID, sig_a, sig_b),
autoOr(NEW_ID, group_sig_a, group_sig_b));
auto prop_s = autoOr(NEWER_ID,
autoXor(NEWER_ID, sig_a, sig_b),
autoOr(NEWER_ID, group_sig_a, group_sig_b));
auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s);
auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s);
auto prop_a = autoOr(NEWER_ID, autoNot(NEWER_ID, sig_s), group_sig_s);
auto prop_b = autoOr(NEWER_ID, sig_s, group_sig_s);
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto tag_sig_s = tag_signal(tag, sig_s);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a);
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b);
tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s);
tag_sig_a = autoAnd(NEWER_ID, tag_sig_a, prop_a);
tag_sig_b = autoAnd(NEWER_ID, tag_sig_b, prop_b);
tag_sig_s = autoAnd(NEWER_ID, tag_sig_s, prop_s);
auto tag_sig = autoOr(NEW_ID, tag_sig_s,
autoOr(NEW_ID, tag_sig_a, tag_sig_b));
auto tag_sig = autoOr(NEWER_ID, tag_sig_s,
autoOr(NEWER_ID, tag_sig_a, tag_sig_b));
emit_tag_signal(tag, sig_y, tag_sig);
return;
}
@ -620,15 +620,15 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b);
// The output can only be affected by the tagged inputs if all group-untagged bits are equal
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
auto masked_b = autoOr(NEW_ID, sig_b, group_sig);
auto masked_a = autoOr(NEWER_ID, sig_a, group_sig);
auto masked_b = autoOr(NEWER_ID, sig_b, group_sig);
auto prop = autoEq(NEW_ID, masked_a, masked_b);
auto prop = autoEq(NEWER_ID, masked_a, masked_b);
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b}));
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -652,15 +652,15 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
auto tag_sig_b = tag_signal(tag, sig_b);
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
auto group_sig = autoOr(NEWER_ID, group_sig_a, group_sig_b);
// The output can only be affected by the tagged inputs if the greatest possible sig_a is
// greater or equal to the least possible sig_b
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig));
auto masked_a = autoOr(NEWER_ID, sig_a, group_sig);
auto masked_b = autoAnd(NEWER_ID, sig_b, autoNot(NEWER_ID, group_sig));
auto prop = autoGe(NEW_ID, masked_a, masked_b);
auto prop = autoGe(NEWER_ID, masked_a, masked_b);
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
auto tag_sig = autoAnd(NEWER_ID, prop, autoReduceOr(NEWER_ID, {tag_sig_a, tag_sig_b}));
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -674,13 +674,13 @@ struct DftTagWorker {
auto tag_sig_a = tag_signal(tag, sig_a);
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
sig_a = autoNot(NEW_ID, sig_a);
sig_a = autoNot(NEWER_ID, sig_a);
auto filled = autoOr(NEW_ID, sig_a, group_sig_a);
auto filled = autoOr(NEWER_ID, sig_a, group_sig_a);
auto prop = autoReduceAnd(NEW_ID, filled);
auto tagged = autoReduceOr(NEW_ID, tag_sig_a);
auto tag_sig = autoAnd(NEW_ID, prop, tagged);
auto prop = autoReduceAnd(NEWER_ID, filled);
auto tagged = autoReduceOr(NEWER_ID, tag_sig_a);
auto tag_sig = autoAnd(NEWER_ID, prop, tagged);
tag_sig.extend_u0(GetSize(sig_y), false);
emit_tag_signal(tag, sig_y, tag_sig);
return;
@ -698,10 +698,10 @@ struct DftTagWorker {
auto sig_q = ff.sig_q;
auto sig_d = ff.sig_d;
ff.name = NEW_ID;
ff.name = NEWER_ID;
ff.cell = nullptr;
ff.sig_d = tag_signal(tag, ff.sig_d);
ff.sig_q = module->addWire(NEW_ID, width);
ff.sig_q = module->addWire(NEWER_ID, width);
ff.is_anyinit = false;
ff.val_init = Const(0, width);
ff.emit();
@ -727,7 +727,7 @@ struct DftTagWorker {
}
}
SigBit any_tagged = autoReduceOr(NEW_ID, tag_input);
SigBit any_tagged = autoReduceOr(NEWER_ID, tag_input);
for (auto &conn : cell->connections()) {
if (cell->output(conn.first)) {

2
passes/cmds/glift.cc
View file

@ -144,7 +144,7 @@ private:
//In this case, a nonzero hole metamux select value means less logic.
//Thus we should invert the ReduceOr over the metamux_select signal.
RTLIL::SigSpec pmux_select = module->ReduceOr(metamux_select.as_wire()->name.str() + "_nonzero", metamux_select);
return module->Pmux(NEW_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute());
return module->Pmux(NEWER_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->get_src_attribute());
} else {
auto select_width = metamux_select.as_wire()->width;

2
passes/cmds/portarcs.cc
View file

@ -291,7 +291,7 @@ struct PortarcsPass : Pass {
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++) {
if (p[i] >= 0) {
Cell *spec = m->addCell(NEW_ID, ID($specify2));
Cell *spec = m->addCell(NEWER_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, p[i]);

4
passes/cmds/rename.cc
View file

@ -494,11 +494,11 @@ struct RenamePass : public Pass {
for (auto wire : module->selected_wires())
if (wire->name.isPublic() && wire->port_id == 0)
new_wire_names[wire] = NEW_ID;
new_wire_names[wire] = NEWER_ID;
for (auto cell : module->selected_cells())
if (cell->name.isPublic())
new_cell_names[cell] = NEW_ID;
new_cell_names[cell] = NEWER_ID;
for (auto &it : new_wire_names)
module->rename(it.first, it.second);

2
passes/cmds/scatter.cc
View file

@ -51,7 +51,7 @@ struct ScatterPass : public Pass {
for (auto cell : module->cells()) {
dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEWER_ID, GetSize(conn.second))));
for (auto &it : new_connections) {
if (ct.cell_output(cell->type, it.first))
module->connect(RTLIL::SigSig(it.second.first, it.second.second));

8
passes/cmds/setundef.cc
View file

@ -345,9 +345,9 @@ struct SetundefPass : public Pass {
for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ)
bits = module->Anyseq(NEW_ID, c.width);
bits = module->Anyseq(NEWER_ID, c.width);
else if (worker.next_bit_mode == MODE_ANYCONST)
bits = module->Anyconst(NEW_ID, c.width);
bits = module->Anyconst(NEWER_ID, c.width);
else
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
@ -530,9 +530,9 @@ struct SetundefPass : public Pass {
if (width > 0) {
if (worker.next_bit_mode == MODE_ANYSEQ)
sig.replace(cursor, module->Anyseq(NEW_ID, width));
sig.replace(cursor, module->Anyseq(NEWER_ID, width));
else
sig.replace(cursor, module->Anyconst(NEW_ID, width));
sig.replace(cursor, module->Anyconst(NEWER_ID, width));
cursor += width;
} else {
cursor++;

10
passes/cmds/splice.cc
View file

@ -75,12 +75,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
}
@ -132,12 +132,12 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
cell->setPort(ID::Y, module->addWire(NEWER_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
}
@ -232,7 +232,7 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
RTLIL::IdString orig_name = it.first->name;
module->rename(it.first, NEW_ID);
module->rename(it.first, NEWER_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;

178
passes/cmds/xprop.cc
View file

@ -55,18 +55,18 @@ struct XpropWorker
Module *module;
void invert() { std::swap(is_0, is_1); }
void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_ID, is_1, is_x))); }
void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_x))); }
void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_1))); }
void auto_0() { connect_0(module->Not(NEWER_ID, module->Or(NEWER_ID, is_1, is_x))); }
void auto_1() { connect_1(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_x))); }
void auto_x() { connect_x(module->Not(NEWER_ID, module->Or(NEWER_ID, is_0, is_1))); }
void connect_0(SigSpec sig) { module->connect(is_0, sig); }
void connect_1(SigSpec sig) { module->connect(is_1, sig); }
void connect_x(SigSpec sig) { module->connect(is_x, sig); }
void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); }
void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_x))); }
void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_ID, is_0))); }
void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEWER_ID, sig, module->Not(NEWER_ID, is_0))); }
void connect_as_bool() {
int width = GetSize(is_0);
@ -198,13 +198,13 @@ struct XpropWorker
}
if (!invert.empty() && !driving)
invert = module->Not(NEW_ID, invert);
invert = module->Not(NEWER_ID, invert);
EncodedSig new_sigs;
if (new_bits > 0) {
new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
new_sigs.is_x = module->addWire(NEW_ID, new_bits);
new_sigs.is_0 = module->addWire(NEWER_ID, new_bits);
new_sigs.is_1 = module->addWire(NEWER_ID, new_bits);
new_sigs.is_x = module->addWire(NEWER_ID, new_bits);
}
int invert_pos = 0;
@ -253,7 +253,7 @@ struct XpropWorker
}
if (!driven_orig.empty()) {
auto decoder = module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
auto decoder = module->addBwmux(NEWER_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
decoder->set_bool_attribute(ID::xprop_decoder);
}
if (!driven_never_x.first.empty()) {
@ -261,21 +261,21 @@ struct XpropWorker
}
if (driving && (options.assert_encoding || options.assume_encoding)) {
auto not_0 = module->Not(NEW_ID, result.is_0);
auto not_1 = module->Not(NEW_ID, result.is_1);
auto not_x = module->Not(NEW_ID, result.is_x);
auto valid = module->ReduceAnd(NEW_ID, {
module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)),
module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)),
module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)),
auto not_0 = module->Not(NEWER_ID, result.is_0);
auto not_1 = module->Not(NEWER_ID, result.is_1);
auto not_x = module->Not(NEWER_ID, result.is_x);
auto valid = module->ReduceAnd(NEWER_ID, {
module->Eq(NEWER_ID, result.is_0, module->And(NEWER_ID, not_1, not_x)),
module->Eq(NEWER_ID, result.is_1, module->And(NEWER_ID, not_0, not_x)),
module->Eq(NEWER_ID, result.is_x, module->And(NEWER_ID, not_0, not_1)),
});
if (options.assert_encoding)
module->addAssert(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
module->addAssert(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1);
else
module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
module->addAssume(NEWER_ID_SUFFIX("xprop_enc"), valid, State::S1);
if (options.debug_asserts) {
auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1);
auto bad_bits = module->Bweqx(NEWER_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
module->addAssert(NEWER_ID_SUFFIX("xprop_debug"), module->LogicNot(NEWER_ID, bad_bits), State::S1);
}
}
@ -543,8 +543,8 @@ struct XpropWorker
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
enc_b.invert();
enc_y.connect_0(module->Or(NEW_ID, enc_a.is_0, enc_b.is_0));
enc_y.connect_1(module->And(NEW_ID, enc_a.is_1, enc_b.is_1));
enc_y.connect_0(module->Or(NEWER_ID, enc_a.is_0, enc_b.is_0));
enc_y.connect_1(module->And(NEWER_ID, enc_a.is_1, enc_b.is_1));
enc_y.auto_x();
module->remove(cell);
return;
@ -564,8 +564,8 @@ struct XpropWorker
if (cell->type == ID($logic_not))
enc_a.invert();
enc_y.connect_0(module->ReduceOr(NEW_ID, enc_a.is_0));
enc_y.connect_1(module->ReduceAnd(NEW_ID, enc_a.is_1));
enc_y.connect_0(module->ReduceOr(NEWER_ID, enc_a.is_0));
enc_y.connect_1(module->ReduceAnd(NEWER_ID, enc_a.is_1));
enc_y.auto_x();
module->remove(cell);
@ -584,8 +584,8 @@ struct XpropWorker
enc_y.invert();
enc_y.connect_x(module->ReduceOr(NEW_ID, enc_a.is_x));
enc_y.connect_1_under_x(module->ReduceXor(NEW_ID, enc_a.is_1));
enc_y.connect_x(module->ReduceOr(NEWER_ID, enc_a.is_x));
enc_y.connect_1_under_x(module->ReduceXor(NEWER_ID, enc_a.is_1));
enc_y.auto_0();
module->remove(cell);
@ -603,16 +603,16 @@ struct XpropWorker
enc_y.connect_as_bool();
auto a_is_1 = module->ReduceOr(NEW_ID, enc_a.is_1);
auto a_is_0 = module->ReduceAnd(NEW_ID, enc_a.is_0);
auto b_is_1 = module->ReduceOr(NEW_ID, enc_b.is_1);
auto b_is_0 = module->ReduceAnd(NEW_ID, enc_b.is_0);
auto a_is_1 = module->ReduceOr(NEWER_ID, enc_a.is_1);
auto a_is_0 = module->ReduceAnd(NEWER_ID, enc_a.is_0);
auto b_is_1 = module->ReduceOr(NEWER_ID, enc_b.is_1);
auto b_is_0 = module->ReduceAnd(NEWER_ID, enc_b.is_0);
if (cell->type == ID($logic_or))
enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
enc_y.connect_0(module->Or(NEW_ID, a_is_0, b_is_0));
enc_y.connect_1(module->And(NEW_ID, a_is_1, b_is_1));
enc_y.connect_0(module->Or(NEWER_ID, a_is_0, b_is_0));
enc_y.connect_1(module->And(NEWER_ID, a_is_1, b_is_1));
enc_y.auto_x();
module->remove(cell);
return;
@ -634,8 +634,8 @@ struct XpropWorker
if (cell->type.in(ID($xnor), ID($_XNOR_)))
enc_y.invert();
enc_y.connect_x(module->Or(NEW_ID, enc_a.is_x, enc_b.is_x));
enc_y.connect_1_under_x(module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1));
enc_y.connect_x(module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x));
enc_y.connect_1_under_x(module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1));
enc_y.auto_0();
module->remove(cell);
return;
@ -657,11 +657,11 @@ struct XpropWorker
if (cell->type == ID($ne))
enc_y.invert();
auto delta = module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1);
auto xpos = module->Or(NEW_ID, enc_a.is_x, enc_b.is_x);
auto delta = module->Xor(NEWER_ID, enc_a.is_1, enc_b.is_1);
auto xpos = module->Or(NEWER_ID, enc_a.is_x, enc_b.is_x);
enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_ID, xpos))));
enc_y.connect_x_under_0(module->ReduceOr(NEW_ID, xpos));
enc_y.connect_0(module->ReduceOr(NEWER_ID, module->And(NEWER_ID, delta, module->Not(NEWER_ID, xpos))));
enc_y.connect_x_under_0(module->ReduceOr(NEWER_ID, xpos));
enc_y.auto_1();
module->remove(cell);
return;
@ -678,12 +678,12 @@ struct XpropWorker
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1);
auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1});
auto eq = module->ReduceAnd(NEWER_ID, {delta_0, delta_1});
auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq;
auto res = cell->type == ID($nex) ? module->Not(NEWER_ID, eq) : eq;
module->connect(sig_y[0], res);
if (GetSize(sig_y) > 1)
@ -700,9 +700,9 @@ struct XpropWorker
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
module->addAnd(NEW_ID, delta_0, delta_1, sig_y);
auto delta_0 = module->Xnor(NEWER_ID, enc_a.is_0, enc_b.is_0);
auto delta_1 = module->Xnor(NEWER_ID, enc_a.is_1, enc_b.is_1);
module->addAnd(NEWER_ID, delta_0, delta_1, sig_y);
module->remove(cell);
return;
}
@ -721,12 +721,12 @@ struct XpropWorker
auto enc_s = encoded(sig_s);
auto enc_y = encoded(sig_y, true);
enc_y.connect_1(module->And(NEW_ID,
module->Or(NEW_ID, enc_a.is_1, enc_s.is_1),
module->Or(NEW_ID, enc_b.is_1, enc_s.is_0)));
enc_y.connect_0(module->And(NEW_ID,
module->Or(NEW_ID, enc_a.is_0, enc_s.is_1),
module->Or(NEW_ID, enc_b.is_0, enc_s.is_0)));
enc_y.connect_1(module->And(NEWER_ID,
module->Or(NEWER_ID, enc_a.is_1, enc_s.is_1),
module->Or(NEWER_ID, enc_b.is_1, enc_s.is_0)));
enc_y.connect_0(module->And(NEWER_ID,
module->Or(NEWER_ID, enc_a.is_0, enc_s.is_1),
module->Or(NEWER_ID, enc_b.is_0, enc_s.is_0)));
enc_y.auto_x();
module->remove(cell);
return;
@ -745,23 +745,23 @@ struct XpropWorker
int width = GetSize(enc_y);
auto all_x = module->ReduceOr(NEW_ID, {
auto all_x = module->ReduceOr(NEWER_ID, {
enc_s.is_x,
module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width)))
module->And(NEWER_ID, enc_s.is_1, module->Sub(NEWER_ID, enc_s.is_1, Const(1, width)))
});
auto selected = enc_a;
for (int i = 0; i < GetSize(enc_s); i++) {
auto sel_bit = enc_s.is_1[i];
selected.is_0 = module->Mux(NEW_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit);
selected.is_1 = module->Mux(NEW_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit);
selected.is_x = module->Mux(NEW_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit);
selected.is_0 = module->Mux(NEWER_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit);
selected.is_1 = module->Mux(NEWER_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit);
selected.is_x = module->Mux(NEWER_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit);
}
enc_y.connect_0(module->Mux(NEW_ID, selected.is_0, Const(State::S0, width), all_x));
enc_y.connect_1(module->Mux(NEW_ID, selected.is_1, Const(State::S0, width), all_x));
enc_y.connect_x(module->Mux(NEW_ID, selected.is_x, Const(State::S1, width), all_x));
enc_y.connect_0(module->Mux(NEWER_ID, selected.is_0, Const(State::S0, width), all_x));
enc_y.connect_1(module->Mux(NEWER_ID, selected.is_1, Const(State::S0, width), all_x));
enc_y.connect_x(module->Mux(NEWER_ID, selected.is_x, Const(State::S1, width), all_x));
module->remove(cell);
return;
@ -776,12 +776,12 @@ struct XpropWorker
auto enc_b = encoded(sig_b);
auto enc_y = encoded(sig_y, true);
auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEW_ID, all_x)[0];
auto all_x = module->ReduceOr(NEWER_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEWER_ID, all_x)[0];
SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_not_0 = module->addWire(NEWER_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEWER_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEWER_ID, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
@ -789,32 +789,32 @@ struct XpropWorker
std::swap(enc_a.is_0, enc_a.is_x);
}
auto shift_0 = module->addCell(NEW_ID, encoded_type);
auto shift_0 = module->addCell(NEWER_ID, encoded_type);
shift_0->parameters = cell->parameters;
shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(ID::A, module->Not(NEWER_ID, enc_a.is_0));
shift_0->setPort(ID::B, enc_b.is_1);
shift_0->setPort(ID::Y, y_not_0);
auto shift_1 = module->addCell(NEW_ID, encoded_type);
auto shift_1 = module->addCell(NEWER_ID, encoded_type);
shift_1->parameters = cell->parameters;
shift_1->setPort(ID::A, enc_a.is_1);
shift_1->setPort(ID::B, enc_b.is_1);
shift_1->setPort(ID::Y, y_1);
auto shift_x = module->addCell(NEW_ID, encoded_type);
auto shift_x = module->addCell(NEWER_ID, encoded_type);
shift_x->parameters = cell->parameters;
shift_x->setPort(ID::A, enc_a.is_x);
shift_x->setPort(ID::B, enc_b.is_1);
shift_x->setPort(ID::Y, y_x);
SigSpec y_0 = module->Not(NEW_ID, y_not_0);
SigSpec y_0 = module->Not(NEWER_ID, y_not_0);
if (cell->type == ID($shiftx))
std::swap(y_0, y_x);
enc_y.connect_0(module->And(NEW_ID, y_0, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_1(module->And(NEW_ID, y_1, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_x(module->Or(NEW_ID, y_x, SigSpec(all_x, GetSize(sig_y))));
enc_y.connect_0(module->And(NEWER_ID, y_0, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_1(module->And(NEWER_ID, y_1, SigSpec(not_all_x, GetSize(sig_y))));
enc_y.connect_x(module->Or(NEWER_ID, y_x, SigSpec(all_x, GetSize(sig_y))));
module->remove(cell);
return;
@ -838,10 +838,10 @@ struct XpropWorker
auto enc_d = encoded(sig_d);
auto enc_q = encoded(sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
auto data_q = module->addWire(NEWER_ID, GetSize(sig_q));
module->addFf(NEW_ID, enc_d.is_1, data_q);
module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
module->addFf(NEWER_ID, enc_d.is_1, data_q);
module->addFf(NEWER_ID, enc_d.is_x, enc_q.is_x);
initvals.set_init(data_q, init_q_is_1);
initvals.set_init(enc_q.is_x, init_q_is_x);
@ -881,14 +881,14 @@ struct XpropWorker
auto enc_d = encoded(ff.sig_d);
auto enc_q = encoded(ff.sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
auto data_q = module->addWire(NEWER_ID, GetSize(ff.sig_q));
ff.sig_d = enc_d.is_1;
ff.sig_q = data_q;
ff.val_init = init_q_is_1;
ff.emit();
ff.name = NEW_ID;
ff.name = NEWER_ID;
ff.cell = nullptr;
ff.sig_d = enc_d.is_x;
ff.sig_q = enc_q.is_x;
@ -925,13 +925,13 @@ struct XpropWorker
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto sig_b = cell->getPort(ID::B);
auto invalid = module->LogicNot(NEW_ID, sig_b);
auto invalid = module->LogicNot(NEWER_ID, sig_b);
inbits_x.append(invalid);
sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
sig_b[0] = module->Or(NEWER_ID, sig_b[0], invalid);
cell->setPort(ID::B, sig_b);
}
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEWER_ID, inbits_x));
bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
@ -941,7 +941,7 @@ struct XpropWorker
if (bool_out)
enc_port.connect_as_bool();
SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
SigSpec new_output = module->addWire(NEWER_ID, GetSize(conn.second));
enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));
@ -999,7 +999,7 @@ struct XpropWorker
if (options.split_public) {
// Need to hide the original wire so split_public doesn't try to split it again
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str()));
}
} else {
auto enc = encoded(wire, true);
@ -1052,7 +1052,7 @@ struct XpropWorker
module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x);
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
module->rename(wire, NEWER_ID_SUFFIX(wire->name.c_str()));
}
}
@ -1092,9 +1092,9 @@ struct XpropWorker
it->second.driven = true;
}
module->addBweqx(NEW_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0);
module->addBweqx(NEW_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1);
module->addBweqx(NEW_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x);
module->addBweqx(NEWER_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0);
module->addBweqx(NEWER_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1);
module->addBweqx(NEWER_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x);
}
}
};
@ -1230,7 +1230,7 @@ struct XpropPass : public Pass {
continue;
if (wire->port_input) {
module->addAssume(NEW_ID, module->Not(NEW_ID, module->ReduceOr(NEW_ID, module->Bweqx(NEW_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1);
module->addAssume(NEWER_ID, module->Not(NEWER_ID, module->ReduceOr(NEWER_ID, module->Bweqx(NEWER_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1);
}
}
}