mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 06:13:41 +00:00
Code Activity

verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

Browse source 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
This commit is contained in:
Zachary Snow 2024-02-11 13:28:14 -05:00 • committed by Martin Povišer
parent 55595b6c8d
commit 73cf658996
6 changed files with 72 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

6
frontends/ast/simplify.cc
View file

@ -1292,6 +1292,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
else if (contains_unbased_unsized(value))
// unbased unsized literals extend to width of the context
lookup_suggested = true;
else if (value->type == AST_TO_UNSIGNED)
// inner expression may be signed by default
lookup_suggested = true;
else if (value->type == AST_CONCAT && value->children.size() == 1)
// concat of a single expression is equivalent to $unsigned
lookup_suggested = true;
}
}