verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

frontends/ast/genrtlil.cc

@@ -2124,11 +2124,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						if (sig.is_wire()) {
 							// if the resulting SigSpec is a wire, its
 							// signedness should match that of the AstNode
-							if (arg->type == AST_IDENTIFIER && arg->id2ast && arg->id2ast->is_signed && !arg->is_signed)
-								// fully-sliced signed wire will be resolved
-								// once the module becomes available
-								log_assert(attributes.count(ID::reprocess_after));
-							else
+							// unless this instantiation depends on module
+							// information that isn't available yet
+							if (!attributes.count(ID::reprocess_after))
 								log_assert(arg->is_signed == sig.as_wire()->is_signed);
 						} else if (arg->is_signed) {
 							// non-trivial signed nodes are indirected through

frontends/ast/simplify.cc

@@ -1292,6 +1292,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 				else if (contains_unbased_unsized(value))
 					// unbased unsized literals extend to width of the context
 					lookup_suggested = true;
+				else if (value->type == AST_TO_UNSIGNED)
+					// inner expression may be signed by default
+					lookup_suggested = true;
+				else if (value->type == AST_CONCAT && value->children.size() == 1)
+					// concat of a single expression is equivalent to $unsigned
+					lookup_suggested = true;
 			}
 		}