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verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

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- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
This commit is contained in:
Zachary Snow 2024-02-11 13:28:14 -05:00 • committed by Martin Povišer
parent 55595b6c8d
commit 73cf658996
6 changed files with 72 additions and 9 deletions
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CHANGELOG
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@ -4,6 +4,11 @@ List of major changes and improvements between releases
Yosys 0.50 .. Yosys 0.51-dev
--------------------------
* Verilog
- Fixed an issue that prevented using `{<expr>}` or `$unsigned(<expr>)` for
certain signed expressions in port connections
- Fixed an issue that prevented writing to a memory word via a concatenation
in an output port connection
Yosys 0.49 .. Yosys 0.50
--------------------------