Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046

tests/opt/opt_ff_sat.v

@@ -0,0 +1,15 @@
+module top(
+					 input 	clk,
+					 input 	a,
+					 output b
+					 );
+  reg 						b_reg;
+  initial begin
+    b_reg <= 0;
+  end
+
+  assign b = b_reg;
+  always @(posedge clk) begin
+    b_reg <= a && b_reg;
+  end
+endmodule

tests/opt/opt_ff_sat.ys

@@ -0,0 +1,4 @@
+read_verilog opt_ff_sat.v
+prep -flatten
+opt_rmdff -sat
+synth