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https://github.com/YosysHQ/yosys
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Refine memory support to deal with general Verilog memory definitions.
This commit is contained in:
Jim Lawson
parent
22035c20ff
commit
73b87e7807
1 changed files with 173 additions and 30 deletions
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@ -106,6 +106,95 @@ struct FirrtlWorker
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RTLIL::Design *design;
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std::string indent;
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// Define read/write ports and memories.
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// We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
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// For the moment, we don't handle $readmemh or $readmemb.
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// These will be part of a subsequent PR.
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struct read_port {
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string name;
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bool clk_enable;
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bool clk_parity;
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bool transparent;
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RTLIL::SigSpec clk;
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RTLIL::SigSpec ena;
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RTLIL::SigSpec addr;
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read_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr) : name(name), clk_enable(clk_enable), clk_parity(clk_parity), transparent(transparent), clk(clk), ena(ena), addr(addr) {
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// Current (3/13/2019) conventions:
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// generate a constant 0 for clock and a constant 1 for enable if they are undefined.
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if (!clk.is_fully_def())
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this->clk = SigSpec(RTLIL::Const(0, 1));
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if (!ena.is_fully_def())
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this->ena = SigSpec(RTLIL::Const(1, 1));
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}
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string gen_read(const char * indent) {
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string addr_expr = make_expr(addr);
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string ena_expr = make_expr(ena);
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string clk_expr = make_expr(clk);
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string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
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string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
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string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
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return addr_str + ena_str + clk_str;
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}
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};
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struct write_port : read_port {
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RTLIL::SigSpec mask;
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write_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr, RTLIL::SigSpec mask) : read_port(name, clk_enable, clk_parity, transparent, clk, ena, addr), mask(mask) {
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if (!clk.is_fully_def())
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this->clk = SigSpec(RTLIL::Const(0));
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if (!ena.is_fully_def())
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this->ena = SigSpec(RTLIL::Const(0));
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if (!mask.is_fully_def())
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this->ena = SigSpec(RTLIL::Const(1));
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}
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string gen_read(const char * /* indent */) {
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log_error("gen_read called on write_port: %s\n", name.c_str());
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return stringf("gen_read called on write_port: %s\n", name.c_str());
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}
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string gen_write(const char * indent) {
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string addr_expr = make_expr(addr);
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string ena_expr = make_expr(ena);
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string clk_expr = make_expr(clk);
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string mask_expr = make_expr(mask);
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string mask_str = stringf("%s%s.mask <= %s\n", indent, name.c_str(), mask_expr.c_str());
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string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
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string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
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string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
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return addr_str + ena_str + clk_str + mask_str;
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}
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};
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/* Memories defined within this module. */
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struct memory {
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string name; // memory name
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int abits; // number of address bits
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int size; // size (in units) of the memory
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int width; // size (in bits) of each element
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int read_latency;
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int write_latency;
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vector<read_port> read_ports;
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vector<write_port> write_ports;
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std::string init_file;
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std::string init_file_srcFileSpec;
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memory(string name, int abits, int size, int width) : name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {}
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memory() : read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
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void add_memory_read_port(read_port &rp) {
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read_ports.push_back(rp);
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}
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void add_memory_write_port(write_port &wp) {
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write_ports.push_back(wp);
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}
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void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) {
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this->init_file = init_file;
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this->init_file_srcFileSpec = init_file_srcFileSpec;
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}
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};
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dict<string, memory> memories;
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void register_memory(memory &m)
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{
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memories[m.name] = m;
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}
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void register_reverse_wire_map(string id, SigSpec sig)
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{
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for (int i = 0; i < GetSize(sig); i++)
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@ -116,7 +205,7 @@ struct FirrtlWorker
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{
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}
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string make_expr(const SigSpec &sig)
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static string make_expr(const SigSpec &sig)
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{
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string expr;
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@ -515,6 +604,7 @@ struct FirrtlWorker
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int abits = cell->parameters.at("\\ABITS").as_int();
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int width = cell->parameters.at("\\WIDTH").as_int();
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int size = cell->parameters.at("\\SIZE").as_int();
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memory m(mem_id, abits, size, width);
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int rd_ports = cell->parameters.at("\\RD_PORTS").as_int();
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int wr_ports = cell->parameters.at("\\WR_PORTS").as_int();
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@ -531,33 +621,24 @@ struct FirrtlWorker
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if (offset != 0)
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log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
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cell_exprs.push_back(stringf(" mem %s:\n", mem_id.c_str()));
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cell_exprs.push_back(stringf(" data-type => UInt<%d>\n", width));
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cell_exprs.push_back(stringf(" depth => %d\n", size));
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for (int i = 0; i < rd_ports; i++)
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cell_exprs.push_back(stringf(" reader => r%d\n", i));
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for (int i = 0; i < wr_ports; i++)
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cell_exprs.push_back(stringf(" writer => w%d\n", i));
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cell_exprs.push_back(stringf(" read-latency => 0\n"));
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cell_exprs.push_back(stringf(" write-latency => 1\n"));
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cell_exprs.push_back(stringf(" read-under-write => undefined\n"));
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for (int i = 0; i < rd_ports; i++)
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{
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if (rd_clk_enable[i] != State::S0)
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log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
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SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width);
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string addr_expr = make_expr(cell->getPort("\\RD_ADDR").extract(i*abits, abits));
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cell_exprs.push_back(stringf(" %s.r%d.addr <= %s\n", mem_id.c_str(), i, addr_expr.c_str()));
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cell_exprs.push_back(stringf(" %s.r%d.en <= UInt<1>(1)\n", mem_id.c_str(), i));
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cell_exprs.push_back(stringf(" %s.r%d.clk <= asClock(UInt<1>(0))\n", mem_id.c_str(), i));
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register_reverse_wire_map(stringf("%s.r%d.data", mem_id.c_str(), i), data_sig);
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string addr_expr = make_expr(addr_sig);
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string name(stringf("%s.r%d", m.name.c_str(), i));
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bool clk_enable = false;
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bool clk_parity = true;
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bool transparency = false;
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SigSpec ena_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
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SigSpec clk_sig = RTLIL::SigSpec(RTLIL::State::S0, 1);
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read_port rp(name, clk_enable, clk_parity, transparency, clk_sig, ena_sig, addr_sig);
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m.add_memory_read_port(rp);
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cell_exprs.push_back(rp.gen_read(indent.c_str()));
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register_reverse_wire_map(stringf("%s.data", name.c_str()), data_sig);
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}
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for (int i = 0; i < wr_ports; i++)
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@ -568,9 +649,16 @@ struct FirrtlWorker
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if (wr_clk_polarity[i] != State::S1)
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log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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string addr_expr = make_expr(cell->getPort("\\WR_ADDR").extract(i*abits, abits));
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string data_expr = make_expr(cell->getPort("\\WR_DATA").extract(i*width, width));
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string clk_expr = make_expr(cell->getPort("\\WR_CLK").extract(i));
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string name(stringf("%s.w%d", m.name.c_str(), i));
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bool clk_enable = true;
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bool clk_parity = true;
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bool transparency = false;
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SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits);
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string addr_expr = make_expr(addr_sig);
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SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width);
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string data_expr = make_expr(data_sig);
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SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i);
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string clk_expr = make_expr(clk_sig);
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SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width);
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string wen_expr = make_expr(wen_sig[0]);
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@ -579,13 +667,50 @@ struct FirrtlWorker
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if (wen_sig[0] != wen_sig[i])
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log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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cell_exprs.push_back(stringf(" %s.w%d.addr <= %s\n", mem_id.c_str(), i, addr_expr.c_str()));
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cell_exprs.push_back(stringf(" %s.w%d.data <= %s\n", mem_id.c_str(), i, data_expr.c_str()));
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cell_exprs.push_back(stringf(" %s.w%d.en <= %s\n", mem_id.c_str(), i, wen_expr.c_str()));
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cell_exprs.push_back(stringf(" %s.w%d.mask <= UInt<1>(1)\n", mem_id.c_str(), i));
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cell_exprs.push_back(stringf(" %s.w%d.clk <= asClock(%s)\n", mem_id.c_str(), i, clk_expr.c_str()));
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SigSpec mask_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
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write_port wp(name, clk_enable, clk_parity, transparency, clk_sig, wen_sig[0], addr_sig, mask_sig);
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m.add_memory_write_port(wp);
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cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), name.c_str(), data_expr.c_str()));
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cell_exprs.push_back(wp.gen_write(indent.c_str()));
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}
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register_memory(m);
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continue;
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}
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if (cell->type.in("$memwr", "$memrd", "$meminit"))
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{
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std::string cell_type = fid(cell->type);
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std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string());
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memory *mp = nullptr;
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if (cell->type == "$meminit" ) {
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log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
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} else {
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// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
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auto addrSig = cell->getPort("\\ADDR");
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auto dataSig = cell->getPort("\\DATA");
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auto enableSig = cell->getPort("\\EN");
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auto clockSig = cell->getPort("\\CLK");
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Const clk_enable = cell->parameters.at("\\CLK_ENABLE");
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Const clk_polarity = cell->parameters.at("\\CLK_POLARITY");
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mp = &memories.at(mem_id);
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int portNum = 0;
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bool transparency = false;
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string data_expr = make_expr(dataSig);
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if (cell->type.in("$memwr")) {
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portNum = (int) mp->write_ports.size();
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write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
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mp->add_memory_write_port(wp);
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cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
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cell_exprs.push_back(wp.gen_write(indent.c_str()));
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} else if (cell->type.in("$memrd")) {
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portNum = (int) mp->read_ports.size();
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read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
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mp->add_memory_read_port(rp);
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cell_exprs.push_back(rp.gen_read(indent.c_str()));
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register_reverse_wire_map(stringf("%s.data", rp.name.c_str()), dataSig);
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}
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}
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continue;
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}
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@ -763,6 +888,24 @@ struct FirrtlWorker
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f << stringf("\n");
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// If we have any memory definitions, output them.
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for (auto kv : memories) {
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memory m = kv.second;
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f << stringf(" mem %s:\n", m.name.c_str());
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f << stringf(" data-type => UInt<%d>\n", m.width);
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f << stringf(" depth => %d\n", m.size);
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for (int i = 0; i < (int) m.read_ports.size(); i += 1) {
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f << stringf(" reader => r%d\n", i);
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}
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for (int i = 0; i < (int) m.write_ports.size(); i += 1) {
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f << stringf(" writer => w%d\n", i);
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}
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f << stringf(" read-latency => %d\n", m.read_latency);
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f << stringf(" write-latency => %d\n", m.write_latency);
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f << stringf(" read-under-write => undefined\n");
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}
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f << stringf("\n");
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for (auto str : cell_exprs)
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f << str;
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