From 6c427d36dd682b97da5f94cd7f0e261ad0802eef Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 24 Sep 2019 18:08:59 +0200 Subject: [PATCH 1/2] Add "portlist" command Signed-off-by: Clifford Wolf --- passes/cmds/Makefile.inc | 1 + passes/cmds/portlist.cc | 76 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 passes/cmds/portlist.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index c8067a8be..cf9663d1d 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o OBJS += passes/cmds/check.o OBJS += passes/cmds/qwp.o OBJS += passes/cmds/edgetypes.o +OBJS += passes/cmds/portlist.o OBJS += passes/cmds/chformal.o OBJS += passes/cmds/chtype.o OBJS += passes/cmds/blackbox.o diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc new file mode 100644 index 000000000..6eedfbbf6 --- /dev/null +++ b/passes/cmds/portlist.cc @@ -0,0 +1,76 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct PortlistPass : public Pass { + PortlistPass() : Pass("portlist", "list (top-level) ports") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" portlist [options] [selection]\n"); + log("\n"); + log("This command lists all module ports found in the selected modules.\n"); + log("\n"); + log("If no selection is provided then it lists the ports on the top module.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + // if (args[argidx] == "-ltr") { + // config.ltr = true; + // continue; + // } + break; + } + + auto handle_module = [&](RTLIL::Module *module) { + for (auto port : module->ports) { + auto *w = module->wire(port); + log("%s [%d:%d] %s\n", w->port_input ? w->port_output ? "inout" : "input" : "output", + w->upto ? w->start_offset : w->start_offset + w->width - 1, + w->upto ? w->start_offset + w->width - 1 : w->start_offset, + log_id(w)); + } + }; + + if (argidx == args.size()) + { + auto *top = design->top_module(); + if (top == nullptr) + log_error("Can't find top module in current design!\n"); + handle_module(top); + } + else + { + extra_args(args, argidx, design); + for (auto module : design->selected_modules()) + handle_module(module); + } + } +} PortlistPass; + +PRIVATE_NAMESPACE_END From b432c9b44b6d8033a835695b2a48cc3fe224bdec Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 25 Sep 2019 09:20:38 +0200 Subject: [PATCH 2/2] Improve "portlist" command Signed-off-by: Clifford Wolf --- passes/cmds/portlist.cc | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index 6eedfbbf6..38c4a8597 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -35,33 +35,50 @@ struct PortlistPass : public Pass { log("\n"); log("If no selection is provided then it lists the ports on the top module.\n"); log("\n"); + log(" -m\n"); + log(" print verilog blackbox module definitions instead of port lists\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + bool m_mode = false; + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-ltr") { - // config.ltr = true; - // continue; - // } + if (args[argidx] == "-m") { + m_mode = true; + continue; + } break; } + bool first_module = true; + auto handle_module = [&](RTLIL::Module *module) { + vector ports; + if (first_module) + first_module = false; + else + log("\n"); for (auto port : module->ports) { auto *w = module->wire(port); - log("%s [%d:%d] %s\n", w->port_input ? w->port_output ? "inout" : "input" : "output", - w->upto ? w->start_offset : w->start_offset + w->width - 1, - w->upto ? w->start_offset + w->width - 1 : w->start_offset, - log_id(w)); + ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output", + w->upto ? w->start_offset : w->start_offset + w->width - 1, + w->upto ? w->start_offset + w->width - 1 : w->start_offset, + log_id(w))); } + log("module %s%s\n", log_id(module), m_mode ? " (" : ""); + for (int i = 0; i < GetSize(ports); i++) + log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : ""); + if (m_mode) + log(");\nendmodule\n"); }; if (argidx == args.size()) { auto *top = design->top_module(); if (top == nullptr) - log_error("Can't find top module in current design!\n"); + log_cmd_error("Can't find top module in current design!\n"); handle_module(top); } else