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Added -selected option to various backends

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This commit is contained in:
Clifford Wolf 2013-09-03 19:10:11 +02:00
parent 5059b31660
commit 73914d1a41
3 changed files with 58 additions and 9 deletions
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23
backends/ilang/ilang_backend.cc
View file

@ -342,12 +342,29 @@ struct IlangBackend : public Backend {
log("Write the current design to an 'ilang' file. (ilang is a text representation\n"); log("Write the current design to an 'ilang' file. (ilang is a text representation\n");
log("of a design in yosys's internal format.)\n"); log("of a design in yosys's internal format.)\n");
log("\n"); log("\n");
log(" -selected\n");
log(" only write selected parts of the design.\n");
log("\n");
} }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
bool selected = false;
log_header("Executing ILANG backend.\n"); log_header("Executing ILANG backend.\n");
extra_args(f, filename, args, 1);
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-selected") {
selected = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
log("Output filename: %s\n", filename.c_str()); log("Output filename: %s\n", filename.c_str());
ILANG_BACKEND::dump_design(f, design, false); ILANG_BACKEND::dump_design(f, design, selected);
} }
} IlangBackend; } IlangBackend;

17
backends/intersynth/intersynth.cc
View file

@ -69,6 +69,10 @@ struct IntersynthBackend : public Backend {
log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" inputs or outputs. This option can be used multiple times to specify\n");
log(" more than one library.\n"); log(" more than one library.\n");
log("\n"); log("\n");
log(" -selected\n");
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
log("http://www.clifford.at/intersynth/\n"); log("http://www.clifford.at/intersynth/\n");
log("\n"); log("\n");
} }
@ -80,6 +84,7 @@ struct IntersynthBackend : public Backend {
std::vector<std::string> libfiles; std::vector<std::string> libfiles;
std::vector<RTLIL::Design*> libs; std::vector<RTLIL::Design*> libs;
bool flag_notypes = false; bool flag_notypes = false;
bool selected = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -92,6 +97,10 @@ struct IntersynthBackend : public Backend {
libfiles.push_back(args[++argidx]); libfiles.push_back(args[++argidx]);
continue; continue;
} }
if (args[argidx] == "-selected") {
selected = true;
continue;
}
break; break;
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
@ -123,9 +132,17 @@ struct IntersynthBackend : public Backend {
RTLIL::Module *module = module_it.second; RTLIL::Module *module = module_it.second;
SigMap sigmap(module); SigMap sigmap(module);
if (module->attributes.count("\\placeholder") > 0)
continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
continue; continue;
if (selected && !design->selected_whole_module(module->name)) {
if (design->selected_module(module->name))
log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
continue;
}
log("Generating netlist %s.\n", RTLIL::id2cstr(module->name)); log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));
if (module->memories.size() != 0 || module->processes.size() != 0) if (module->memories.size() != 0 || module->processes.size() != 0)

27
backends/verilog/verilog_backend.cc
View file

@ -928,6 +928,10 @@ struct VerilogBackend : public Backend {
log(" this option set only the modules with the 'placeholder' attribute\n"); log(" this option set only the modules with the 'placeholder' attribute\n");
log(" are written to the output file.\n"); log(" are written to the output file.\n");
log("\n"); log("\n");
log(" -selected\n");
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
} }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{ {
@ -939,6 +943,7 @@ struct VerilogBackend : public Backend {
noexpr = false; noexpr = false;
bool placeholders = false; bool placeholders = false;
bool selected = false;
reg_ct.clear(); reg_ct.clear();
reg_ct.setup_stdcells_mem(); reg_ct.setup_stdcells_mem();
@ -969,17 +974,27 @@ struct VerilogBackend : public Backend {
placeholders = true; placeholders = true;
continue; continue;
} }
if (arg == "-selected") {
selected = true;
continue;
}
break; break;
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if ((it->second->attributes.count("\\placeholder") > 0) == placeholders) { if ((it->second->attributes.count("\\placeholder") > 0) != placeholders)
if (it != design->modules.begin()) continue;
fprintf(f, "\n"); if (selected && !design->selected_whole_module(it->first)) {
log("Dumping module `%s'.\n", it->first.c_str()); if (design->selected_module(it->first))
dump_module(f, "", it->second); log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
continue;
} }
if (it != design->modules.begin())
fprintf(f, "\n");
log("Dumping module `%s'.\n", it->first.c_str());
dump_module(f, "", it->second);
}
reg_ct.clear(); reg_ct.clear();
} }