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Added -selected option to various backends
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parent
5059b31660
commit
73914d1a41
3 changed files with 58 additions and 9 deletions
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@ -928,6 +928,10 @@ struct VerilogBackend : public Backend {
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log(" this option set only the modules with the 'placeholder' attribute\n");
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log(" are written to the output file.\n");
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log("\n");
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log(" -selected\n");
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log(" only write selected modules. modules must be selected entirely or\n");
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log(" not at all.\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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@ -939,6 +943,7 @@ struct VerilogBackend : public Backend {
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noexpr = false;
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bool placeholders = false;
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bool selected = false;
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reg_ct.clear();
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reg_ct.setup_stdcells_mem();
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@ -969,17 +974,27 @@ struct VerilogBackend : public Backend {
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placeholders = true;
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continue;
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}
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if (arg == "-selected") {
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selected = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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for (auto it = design->modules.begin(); it != design->modules.end(); it++)
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if ((it->second->attributes.count("\\placeholder") > 0) == placeholders) {
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if (it != design->modules.begin())
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fprintf(f, "\n");
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log("Dumping module `%s'.\n", it->first.c_str());
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dump_module(f, "", it->second);
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for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
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if ((it->second->attributes.count("\\placeholder") > 0) != placeholders)
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continue;
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if (selected && !design->selected_whole_module(it->first)) {
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if (design->selected_module(it->first))
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log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
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continue;
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}
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if (it != design->modules.begin())
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fprintf(f, "\n");
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log("Dumping module `%s'.\n", it->first.c_str());
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dump_module(f, "", it->second);
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}
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reg_ct.clear();
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}
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