mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Added SIMLIB_NOLUT to simlib.v
This commit is contained in:
		
							parent
							
								
									e24797add0
								
							
						
					
					
						commit
						7370ae01e9
					
				
					 1 changed files with 2 additions and 0 deletions
				
			
		|  | @ -927,6 +927,7 @@ end | ||||||
| endmodule | endmodule | ||||||
| 
 | 
 | ||||||
| // -------------------------------------------------------- | // -------------------------------------------------------- | ||||||
|  | `ifndef SIMLIB_NOLUT | ||||||
| 
 | 
 | ||||||
| module \$lut (I, O); | module \$lut (I, O); | ||||||
| 
 | 
 | ||||||
|  | @ -961,6 +962,7 @@ endgenerate | ||||||
| 
 | 
 | ||||||
| endmodule | endmodule | ||||||
| 
 | 
 | ||||||
|  | `endif | ||||||
| // -------------------------------------------------------- | // -------------------------------------------------------- | ||||||
| 
 | 
 | ||||||
| module \$assert (A, EN); | module \$assert (A, EN); | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue