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read_aiger: also parse abc9_mergeability

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This commit is contained in:
Eddie Hung 2020-01-22 14:21:25 -08:00
parent 8eb5bb258c
commit 73526a6f10
2 changed files with 6 additions and 2 deletions
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7
frontends/aiger/aigerparse.cc
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@ -442,11 +442,13 @@ void AigerReader::parse_xaiger()
}
}
else if (c == 'r') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_debug("flopNum = %u\n", flopNum);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
f.ignore(flopNum * sizeof(uint32_t));
mergeability.reserve(flopNum);
for (unsigned i = 0; i < flopNum; i++)
mergeability.emplace_back(parse_xaiger_literal(f));
}
else if (c == 'n') {
parse_xaiger_literal(f);
@ -774,6 +776,7 @@ void AigerReader::post_process()
auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
ff->setPort("\\D", d);
ff->setPort("\\Q", q);
ff->attributes["\\abc9_mergeability"] = mergeability[i];
}
dict<RTLIL::IdString, int> wideports_cache;

1
frontends/aiger/aigerparse.h
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@ -45,6 +45,7 @@ struct AigerReader
std::vector<RTLIL::Wire*> outputs;
std::vector<RTLIL::Wire*> bad_properties;
std::vector<RTLIL::Cell*> boxes;
std::vector<int> mergeability;
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger();