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sigspec: move construct

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This commit is contained in:
Emil J. Tywoniak 2024-07-17 18:57:47 +02:00
parent 6e3bf76ea4
commit 7325863db2
2 changed files with 13 additions and 36 deletions
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33
kernel/rtlil.cc
View file

@ -4020,28 +4020,6 @@ RTLIL::SigSpec::SigSpec(bool bit)
check(); check();
} }
void RTLIL::SigSpec::switch_to_packed() const
{
// TODO change to debug asserts
// log_assert(!this->packed_);
// log_assert(bits_.size() == 0);
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
that->bits_.~vector();
that->packed_ = true;
(void)new (&that->chunks_) std::vector<SigChunk>();
}
void RTLIL::SigSpec::switch_to_unpacked() const
{
// TODO change to debug asserts
// log_assert(this->packed_);
// log_assert(chunks_.size() == 0);
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
that->chunks_.~vector();
that->packed_ = false;
(void)new (&that->bits_) std::vector<SigBit>();
}
void RTLIL::SigSpec::pack() const void RTLIL::SigSpec::pack() const
{ {
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
@ -4075,8 +4053,9 @@ void RTLIL::SigSpec::pack() const
last_end_offset = bit.offset + 1; last_end_offset = bit.offset + 1;
} }
that->switch_to_packed(); that->bits_.~vector();
that->chunks_.swap(new_chunks); that->packed_ = true;
(void)new (&that->chunks_) std::vector<SigChunk>(std::move(new_chunks));
check(); check();
} }
@ -4096,10 +4075,10 @@ void RTLIL::SigSpec::unpack() const
for (int i = 0; i < c.width; i++) for (int i = 0; i < c.width; i++)
new_bits.emplace_back(c, i); new_bits.emplace_back(c, i);
that->chunks_.clear();
that->hash_ = 0; that->hash_ = 0;
that->switch_to_unpacked(); that->chunks_.~vector();
that->bits_.swap(new_bits); that->packed_ = false;
(void)new (&that->bits_) std::vector<SigBit>(std::move(new_bits));
} }
void RTLIL::SigSpec::updhash() const void RTLIL::SigSpec::updhash() const

16
kernel/rtlil.h
View file

@ -838,7 +838,7 @@ struct RTLIL::SigSpecConstIterator
inline void operator++() { index++; } inline void operator++() { index++; }
}; };
struct RTLIL::SigSpec struct alignas(64) RTLIL::SigSpec
{ {
private: private:
int width_; int width_;
@ -851,8 +851,6 @@ private:
void pack() const; void pack() const;
void unpack() const; void unpack() const;
void switch_to_packed() const;
void switch_to_unpacked() const;
void updhash() const; void updhash() const;
inline bool packed() const { inline bool packed() const {
@ -890,13 +888,13 @@ public:
{ {
if (packed_ != other.packed_) { if (packed_ != other.packed_) {
if (packed_) { if (packed_) {
chunks_.clear(); chunks_.~vector();
switch_to_unpacked(); packed_ = false;
bits_ = other.bits_; (void)new (&bits_) std::vector<SigBit>(other.bits_);
} else { } else {
bits_.clear(); bits_.~vector();
switch_to_packed(); packed_ = true;
chunks_ = other.chunks_; (void)new (&chunks_) std::vector<SigChunk>(other.chunks_);
} }
} else { } else {
if (packed_) if (packed_)