mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-18 20:03:39 +00:00
Code Activity

ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-21 12:14:50 +02:00
parent 4b8d42d22c
commit 73122921f5
22 changed files with 2496 additions and 2615 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil.h
View file

@ -1331,7 +1331,7 @@ struct RTLIL::Design
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
std::vector<AST::AstNode*> verilog_packages, verilog_globals;
std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
std::unique_ptr<define_map_t> verilog_defines;
std::vector<RTLIL::Selection> selection_stack;