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attempt to fix formatting

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Pepijn de Vos 2019-11-25 14:50:34 +01:00
parent 6c79abbf5a
commit 72d03dc910
2 changed files with 292 additions and 292 deletions
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308
techlibs/gowin/cells_map.v
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@ -2,281 +2,281 @@
//All DFF* have INIT, but the hardware is always initialised to the reset //All DFF* have INIT, but the hardware is always initialised to the reset
//value regardless. The parameter is ignored. //value regardless. The parameter is ignored.
// DFFN D Flip-Flop with Negative-Edge Clock // DFFN D Flip-Flop with Negative-Edge Clock
module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
else else
DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
// DFF D Flip-Flop // DFF D Flip-Flop
module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
else else
DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
// DFFE D Flip-Flop with Clock Enable // DFFE D Flip-Flop with Clock Enable
module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
else else
DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
else else
DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable // DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
else else
DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
generate generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1) if (_TECHMAP_WIREINIT_Q_ === 1'b1)
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
else else
DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
endgenerate endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1; wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule endmodule
// DFFR D Flip-Flop with Synchronous Reset // DFFR D Flip-Flop with Synchronous Reset
module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset // DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset // DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset // DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFS D Flip-Flop with Synchronous Set // DFFS D Flip-Flop with Synchronous Set
module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set // DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set // DFFSE D Flip-Flop with Clock Enable and Synchronous Set
module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set // DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFP D Flip-Flop with Asynchronous Preset // DFFP D Flip-Flop with Asynchronous Preset
module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset // DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFC D Flip-Flop with Asynchronous Clear // DFFC D Flip-Flop with Asynchronous Clear
module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear // DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset // DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset // DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear // DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear // DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule endmodule
module \$lut (A, Y); module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0])); .I0(A[0]));
end else end else
if (WIDTH == 2) begin if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1])); .I0(A[0]), .I1(A[1]));
end else end else
if (WIDTH == 3) begin if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2])); .I0(A[0]), .I1(A[1]), .I2(A[2]));
end else end else
if (WIDTH == 4) begin if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else end else
if (WIDTH == 5) begin if (WIDTH == 5) begin
wire f0, f1; wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0)); \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1)); \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y)); MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
end else end else
if (WIDTH == 6) begin if (WIDTH == 6) begin
wire f0, f1; wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0)); \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1)); \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y)); MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
end else end else
if (WIDTH == 7) begin if (WIDTH == 7) begin
wire f0, f1; wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0)); \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1)); \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y)); MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
end else end else
if (WIDTH == 8) begin if (WIDTH == 8) begin
wire f0, f1; wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y)); MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
end else begin end else begin
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
end end
endgenerate endgenerate
endmodule endmodule

276
tests/arch/gowin/init.v
View file

@ -6,108 +6,108 @@ module myDFF (output reg Q, input CLK, D);
endmodule endmodule
module myDFFE (output reg Q, input D, CLK, CE); module myDFFE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK) begin always @(posedge CLK) begin
if (CE) if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFE (positive clock edge; clock enable) endmodule // DFFE (positive clock edge; clock enable)
module myDFFS (output reg Q, input D, CLK, SET); module myDFFS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK) begin always @(posedge CLK) begin
if (SET) if (SET)
Q <= 1'b1; Q <= 1'b1;
else else
Q <= D; Q <= D;
end end
endmodule // DFFS (positive clock edge; synchronous set) endmodule // DFFS (positive clock edge; synchronous set)
module myDFFSE (output reg Q, input D, CLK, CE, SET); module myDFFSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK) begin always @(posedge CLK) begin
if (SET) if (SET)
Q <= 1'b1; Q <= 1'b1;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable) endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
module myDFFR (output reg Q, input D, CLK, RESET); module myDFFR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK) begin always @(posedge CLK) begin
if (RESET) if (RESET)
Q <= 1'b0; Q <= 1'b0;
else else
Q <= D; Q <= D;
end end
endmodule // DFFR (positive clock edge; synchronous reset) endmodule // DFFR (positive clock edge; synchronous reset)
module myDFFRE (output reg Q, input D, CLK, CE, RESET); module myDFFRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK) begin always @(posedge CLK) begin
if (RESET) if (RESET)
Q <= 1'b0; Q <= 1'b0;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable) endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
module myDFFP (output reg Q, input D, CLK, PRESET); module myDFFP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK or posedge PRESET) begin always @(posedge CLK or posedge PRESET) begin
if(PRESET) if(PRESET)
Q <= 1'b1; Q <= 1'b1;
else else
Q <= D; Q <= D;
end end
endmodule // DFFP (positive clock edge; asynchronous preset) endmodule // DFFP (positive clock edge; asynchronous preset)
module myDFFPE (output reg Q, input D, CLK, CE, PRESET); module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK or posedge PRESET) begin always @(posedge CLK or posedge PRESET) begin
if(PRESET) if(PRESET)
Q <= 1'b1; Q <= 1'b1;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable) endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
module myDFFC (output reg Q, input D, CLK, CLEAR); module myDFFC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK or posedge CLEAR) begin always @(posedge CLK or posedge CLEAR) begin
if(CLEAR) if(CLEAR)
Q <= 1'b0; Q <= 1'b0;
else else
Q <= D; Q <= D;
end end
endmodule // DFFC (positive clock edge; asynchronous clear) endmodule // DFFC (positive clock edge; asynchronous clear)
module myDFFCE (output reg Q, input D, CLK, CE, CLEAR); module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(posedge CLK or posedge CLEAR) begin always @(posedge CLK or posedge CLEAR) begin
if(CLEAR) if(CLEAR)
Q <= 1'b0; Q <= 1'b0;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
@ -119,106 +119,106 @@ module myDFFN (output reg Q, input CLK, D);
endmodule endmodule
module myDFFNE (output reg Q, input D, CLK, CE); module myDFFNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK) begin always @(negedge CLK) begin
if (CE) if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFNE (negative clock edge; clock enable) endmodule // DFFNE (negative clock edge; clock enable)
module myDFFNS (output reg Q, input D, CLK, SET); module myDFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK) begin always @(negedge CLK) begin
if (SET) if (SET)
Q <= 1'b1; Q <= 1'b1;
else else
Q <= D; Q <= D;
end end
endmodule // DFFNS (negative clock edge; synchronous set) endmodule // DFFNS (negative clock edge; synchronous set)
module myDFFNSE (output reg Q, input D, CLK, CE, SET); module myDFFNSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK) begin always @(negedge CLK) begin
if (SET) if (SET)
Q <= 1'b1; Q <= 1'b1;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable) endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
module myDFFNR (output reg Q, input D, CLK, RESET); module myDFFNR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK) begin always @(negedge CLK) begin
if (RESET) if (RESET)
Q <= 1'b0; Q <= 1'b0;
else else
Q <= D; Q <= D;
end end
endmodule // DFFNR (negative clock edge; synchronous reset) endmodule // DFFNR (negative clock edge; synchronous reset)
module myDFFNRE (output reg Q, input D, CLK, CE, RESET); module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK) begin always @(negedge CLK) begin
if (RESET) if (RESET)
Q <= 1'b0; Q <= 1'b0;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable) endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
module myDFFNP (output reg Q, input D, CLK, PRESET); module myDFFNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK or posedge PRESET) begin always @(negedge CLK or posedge PRESET) begin
if(PRESET) if(PRESET)
Q <= 1'b1; Q <= 1'b1;
else else
Q <= D; Q <= D;
end end
endmodule // DFFNP (negative clock edge; asynchronous preset) endmodule // DFFNP (negative clock edge; asynchronous preset)
module myDFFNPE (output reg Q, input D, CLK, CE, PRESET); module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK or posedge PRESET) begin always @(negedge CLK or posedge PRESET) begin
if(PRESET) if(PRESET)
Q <= 1'b1; Q <= 1'b1;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable) endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
module myDFFNC (output reg Q, input D, CLK, CLEAR); module myDFFNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK or posedge CLEAR) begin always @(negedge CLK or posedge CLEAR) begin
if(CLEAR) if(CLEAR)
Q <= 1'b0; Q <= 1'b0;
else else
Q <= D; Q <= D;
end end
endmodule // DFFNC (negative clock edge; asynchronous clear) endmodule // DFFNC (negative clock edge; asynchronous clear)
module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR); module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q = INIT; initial Q = INIT;
always @(negedge CLK or posedge CLEAR) begin always @(negedge CLK or posedge CLEAR) begin
if(CLEAR) if(CLEAR)
Q <= 1'b0; Q <= 1'b0;
else if (CE) else if (CE)
Q <= D; Q <= D;
end end
endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable) endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)